PDF1. Introduction
Timing and triggering flexibility is a fundamental part of selecting data acquisition (DAQ) hardware. Instead of a fixed ASIC for controlling device functionality, R Series multifunction RIO devices use an FPGA-based system timing controller to make all analog and digital I/O configurable for application-specific operation. By creating custom DAQ personalities, a single piece of hardware can meet the most demanding requirements and be easily reconfigured for future applications.
Figure 1. PCI-7831R R Series multifunction RIO device.
Using R Series multifunction RIO devices, you can create a custom hardware personality without any prior background or expertise in low-level hardware design. A DAQ “personality” is essentially a LabVIEW FPGA application that has been compiled into a bitfile containing FPGA configuration information. Once the bitfile has been generated, a DAQ personality no longer requires the LabVIEW FPGA Module and can be accessed in LabVIEW for Windows or LabVIEW Real-Time using the NI-RIO driver. The personality can also be downloaded to non-volatile flash memory on the DAQ device itself and configured to load on power-up.
2. Using a Custom DAQ Personality
The LabVIEW FPGA module takes LabVIEW block diagrams implements them to execute in silicon, on an FPGA chip. R Series multifunction RIO hardware is specified in the LabVIEW project explorer, and when the run arrow is pressed, a LabVIEW FPGA VI will begin to compile into a personality bitfile. Once the bitfile has been generated, all front panel objects (controls and indicators) of the LabVIEW FPGA VI are represented as registers on the FPGA chip, and can be accessed from a host application using the NI-RIO driver.
Figure 2 shows the block diagram for a LabVIEW FPGA application that has been compiled into a bitfile, and will be used as the example custom DAQ personality in this tutorial.
Figure 2. Example custom DAQ personality with multi-rate sampling and four 64-bit simple event counters
This example personality samples two analog input channels independently, and also includes four 64-bit simple event counters. Each analog input loop references a separate digital I/O line for triggering, and acquires a finite number of samples upon every rising edge. On R Series multifunction RIO devices, the analog value is digitized when the analog FPGA I/O node executes. The resulting sample is then immediately transferred across the PCI bus to host memory, using a DMA FIFO node. Sampling different analog channels at independent rates is not possible on typical data acquisition hardware.
Figure 3 shows the front panel of the same LabVIEW FPGA VI.
Figure 3. Front Panel for example custom DAQ personality
The front panel controls and indicators are important because they become the only access you have to a compiled LabVIEW FPGA block diagram. As mentioned earlier, all front panel objects are converted to hardware registers on the FPGA. This example uses controls to configure the number of samples and sample period (in microseconds) for the two analog input channels. The 64-bit value of counter registers is also shown on the front panel, and can therefore be read from the host application. The following sections will focus on host application development for this example DAQ personality.
For further information on LabVIEW FPGA programming for data acquisition applications, please see:
Advanced Data Acquisition Techniques with R Series Multifunction RIO
3. Building a Host VI for a compiled LabVIEW FPGA personality
Once the custom DAQ personality has been created, you can interact with hardware registers by developing a host application using the NI-RIO driver. NI-RIO driver software is included with all R Series multifunction RIO hardware, and automatically installs the FPGA Host Interface palette shown in Figure 4.
Figure 4. Open FPGA VI Reference.vi on FPGA Host Interface palette
The Open FPGA VI Reference.vi function on the FPGA Interface palette opens a reference to the R Series board, as well as the LabVIEW FPGA VI, or bitfile.
Figure 5. Selecting a compiled LabVIEW FPGA bitfile
The right-click menu for Open FPGA VI Reference.vi lets you specify a LabVIEW FPGA VI within the LabVIEW project, or browse to a compiled LabVIEW FPGA bitfile. Once the VI or bitfile has been specified, the R Series hardware can be selected. This is also done in the right-click menu by selecting Select Address…, or can be done programmatically by selecting Show Resource Input.
Figure 6. Selecting an R Series target
Next, the Read/Write Control.vi function is used to read or write to any LabVIEW FPGA front panel control or indicator.
Figure 7. Read/Write Control.vi on FPGA Host Interface palette
Once the LabVIEW FPGA VI reference is wired to the input of this function, a list of all front panel controls and indicators is populated, similar to LabVIEW property nodes. Reading this function in a loop will basically use PCI bus transfers to poll registers on the FPGA at the loop rate. The Read/Write Control.vi function is very efficient at passing single data values to and from the compiled LabVIEW FPGA VI.
Figure 8. Writing to FPGA VI front panel objects from the host interface application
A major difference between traditional multifunction DAQ with the NI-DAQmx driver and R Series multifunction RIO is the way that DMA data transfer is implemented. The NI-DAQmx driver will abstract out all transfers from the device to the host computer, while this must be completely programmed in LabVIEW for all FPGA-based hardware. Reading or writing to DMA channels on R Series hardware is accomplished using the Invoke Method.vi function. Once the input of this function is wired with a LabVIEW FPGA VI reference, all DMA channels are populated in the menu list, and can be selected as shown in the figure below.
Figure 9. Invoke Method.vi on FPGA Host Interface palette
The amount of RAM allocated for the Host-side buffer is configured by selecting Configure in the submenu. By default, it is double the size configured on the FPGA.
Reading a DMA FIFO produces an array of unsigned 32-bit integers, as well as the number of elements remaining in the PC buffer. Data must be converted back to signed integer 16 (I16) data type, and scaled accordingly, as shown in the Figure 10.
Figure 10. Scaling data values from DMA FIFOs
For more information on creating DMA FIFOs in LabVIEW FPGA, please see >>
http://zone.ni.com/devzone/cda/tut/p/id/2993
http://zone.ni.com/devzone/cda/tut/p/id/2993#toc6
http://zone.ni.com/devzone/cda/tut/p/id/4534
Finally, the reference must be closed, using the Close FPGA VI Reference.vi function in the FPGA interface palette.
Figure 11. Close FPGA VI Reference.vi on FPGA Host Interface palette
The figure below is the final block diagram for a host application that streams data from an analog input channel and monitors the value of four 64-bit simple event counters.
Figure 12. Block Diagram of final host application VI
Figure 13. Front Panel of final host application VI
You might remember that this example DAQ personality is actually reading two different analog input channels, at two different rates. The following figure is the block diagram of a different host application that reads both analog input loops at different rates.
Figure 14. Block diagram of second host application VI
Figure 15. Front Panel of second host application VI
This shows how many different host applications can be created for the same DAQ personality, depending on what functionality is required.
4. Download Custom DAQ Example Personalities and Documentation
Balanced Analog DAQ
8 analog input channels, 8 analog output channels, 4 counters and 16 digital I/O lines
This custom DAQ personality is a balanced analog I/O board that has 8 simultaneously sampled analog input channels and 8 simultaneous analog output channels. In addition, this personality also includes 4 simple event counters with debounce filtering and 16 static DIO lines.
Click here for the Balanced Analog DAQ Example Personality
Multirate Analog Output
8 analog output channels with multiple update rates
This example DAQ personality uses all 8 analog outputs on R Series PCI and PXI-7833R boards. Each analog output channel can be used in either streaming mode or regeneration mode. In streaming mode, new samples are continuously sent from the host VI to the FPGA and are output as they are received. In regeneration mode, samples are loaded into a block of onboard memory, and the FPGA application continuously indexes through these samples without any further host interaction. This example personality can update groups of analog output channels at different rates, which is not possible with other DAQ devices.
Click here for the Multirate Analog Output Example DAQ Personality
PWM Input and Output
Sixteen Pulse-Width-Modulation (PWM) channels configurable for input or output
The PWM personality was designed to target high channel count needs for both PWM output and input. Currently, there is not a DAQ device capable of more than 4 PWM outputs. The current solution is to use multiple DAQ boards capable of PWM and synchronize their outputs. This personality alleviates that need by customizing a DAQ board to have sixteen PWM channels configurable for input or output. The attached host example code uses 12 PWM outputs and 4 PWM inputs.
Click here for the Pulse Width Modulation Example DAQ Personality
64-bit Counter Board
Sixteen 64-bit simple event counters (40MHz)
This DAQ example personality features sixteen simple-event counters, each with 64-bit resolution. With the ability to count up to 264- 1, these counters can essentially count forever. In addition to being the highest in resolution and channel count, this personality allows users to specify the terminal count, generates output pulses when the terminal count is reached, and provides filtering capability to remove noise and glitches from the source signal.
Click here for the 64-bit Counter Example DAQ Personality
5. Conclusion
While fixed ASIC chips such as the DAQ-STC2 will meet the majority of data acquisition requirements, complete flexibility and customization can be achieved only with the reconfigurable, FPGA-based I/O timing and control of R Series multifunction RIO devices. By creating custom DAQ personalities, a single piece of hardware can meet the most demanding requirements and be easily reconfigured for future applications. The LabVIEW FPGA Module makes triggering and synchronization tasks as simple as graphically drawing the block diagram to do exactly what you need, and once the personality has been compiled it can be accessed from a host application with the NI-RIO driver. Whether it is multirate sampling, custom counter operation, or onboard decision making at 40 MHz, DAQ personalities bring board level customization to commercial off-the-shelf hardware.
