Single Design Environment for Communications System Design

Publish Date: May 22, 2017 | 3 Ratings | 4.00 out of 5 | Print

Overview

To address the complex communications design challenges we face today, designers must evaluate and choose among the wide offering of diverse processing and I/O hardware components and the associated software tools required to program these components. As designers articulate solutions which increasingly require more than one type of processing element, the lack of integration between hardware components and software tools becomes a hindrance to the realization of a prototype.

 

 

LabVIEW Communications eliminates this hurdle by providing a single development environment that can target both multi-core processors and FPGAs, while tightly integrating with the I/O.  Furthermore, LabVIEW Communications scales across multiple heterogeneous systems so designers can define and manage an entire wireless prototyping solution with a single design tool. This approach greatly increases the efficiency of design teams, which no longer need to specialize in a number of different software tools and design flows. Instead, with LabVIEW Communications, design teams can more quickly and efficiently develop on an SDR that contains a processor and FPGA much more quickly than before.  The efficacy of the underlying LabVIEW RIO Architecture as an approach to FPGA based embedded system design has been validated by 3rd party surveys of embedded markets.

An additional benefit of a tool that scales across processors, FPGAs, and I/O is the ability to describe the entire system, including the interactions between components within a single tool. Consequently, this enables full system simulations with substantially less effort, as designers don’t need to stitch simulations across tools to estimate and understand how a system might behave.

While LabVIEW Communications supports a variety of design languages and approaches, including C, .m, and dataflow, the graphical dataflow language is able to span both processor and FPGA seamlessly. The advanced compiler technology within LabVIEW Communications optimizes and handles the mapping of the G dataflow language to the underlying processing component – whether it’s a processor or an FPGA. This provides designers considerable flexibility in experimenting with design partitioning as they can seamlessly move an algorithm or components of an algorithm between the FPGA and the processor.

To ensure a seamless transition of algorithms designed in G between processor and FPGA hardware, LabVIEW Communications also provides built-in tools for data-driven float-to-fixed point conversion. Furthermore, the performance optimizations on the implementation are specific to the underlying hardware.   For example, for a diagram targeted to the processor, LabVIEW Communications is able to properly parallelize and partition a design to automatically utilize the full potential of a multi-core processor, and for a diagram targeted to the FPGA, it is able to accept various user-specified constraints like throughput and clock-rate to properly synthesize a hardware design on the FPGA fabric.

Overall, this ability to quickly partition the design and rapidly iterate on the ideal implementation is only possible with LabVIEW Communications as it offers access to both the FPGA and processor As such, without the hardware integration available in the tool, such design flexibility would be nearly impossible to realize. The benefit to users is the ability to better characterize a design, and to truly understand design tradeoffs which can motivate further refinements. As legions of researchers join the fray to define the next generations of communications standards, tools that enable efficient, rapid innovation on quality software defined radio systems are essential in the race to bring the next disruptive solution to market. It’s no surprise then that LabVIEW Communications System Design Suite and NI SDR hardware is already in the arsenals of those leading the marketplace.

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