NMOS Transistor Characterization with the NI PXIe-4081 7½-Digit DMM

Publish Date: Jan 10, 2018 | 31 Ratings | 3.77 out of 5 | Print

Overview

A field-effect transistor (FET) is a device whose ability to carry current is varied by an applied electronic field; thus, a FET is a voltage controlled device. A Metal-Oxide-Semiconductor FET (MOSFET) is a very common type of FET that is used in integrated circuits and high speed switching applications. MOSFETS are manufactured as enhancement-type or depletion-type and are characterized as an n-channel or p-channel device.

Because MOSFETs can operate at very low current levels, they require high resolution devices to properly test. This document covers the basics of MOSFETs and demonstrates a National Instruments solution for testing an n-channel enhancement-type MOSFET (NMOS).

Table of Contents

  1. NMOS Transistor Basics
  2. Hardware Setup for Testing NMOS
  3. Software Solution for Acquiring Characteristic Curves
  4. Example Program
  5. Other Applications

1. NMOS Transistor Basics

The basic design of an NMOS transistor is provided in Figure 1.


Figure 1: NMOS Transistor

NMOS transistors consist of three terminals: gate, source, and drain. The source is grounded and the device operates by inducing a drain current (iD) as a function of voltages applied at the gate (VGS) and drain (VDS) of the transistor. Every NMOS transistor contains a threshold voltage (Vt) which is constant and unique for each transistor. In order for the transistor to operate, VGS must be greater than Vt. Once this condition has been met, the resulting drain current can be controlled by the voltages supplied at the gate and the drain. The relationship between VGS, VDS, and iD is described by three regions of operation:

1. Cut-off Region: In this region no channel exists (iD = 0) for all values of VD. (VGS < Vt)

2. Ohmic/Triode Region:
The NMOS transistor is active and not “pinched off.” This means the value of VDS affects the value of iD (VGS > Vt and VDS ≤ VGS – Vt). Figure 2 shows the relationship between VGS, VDS, and iD in this region. Notice the linear relationship between iD and VDS. In this region, iD obeys Ohms Law as the NMOS transistor responds as a voltage controlled resistor.


Figure 2: iD vs. VDS (Ohmic/Triode Region)

3. Active/Saturation Region: The channel is “pinched off” because increases in VD have no affect on iD (VGS > Vt and VDS > VGS – Vt). In the saturation region, the amount of drain current is directly related to the values of VGS > Vt.


Figure 3: iD vs. VDS (left) and iD vs. VGS (right)

The two characteristic curves provide important information for engineers implementing NMOS transistors into their system by illustrating whether a particular unit will pass or fail within a certain region of operation. Figure 3 depicts the transition from the triode region into the saturation region given discrete values of VGS and shows the response of iD to changes in VGS while the NMOS transistor is in the saturation region. With enough precision, these curves can be analyzed with a resolution of 1pA.

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2. Hardware Setup for Testing NMOS


Testing the NMOS by acquiring the characteristic curves require a voltage source for both VGS and VD, and a device to measure iD. For the programmable voltage sources, consider using a  Source Measure Unit for optimal precision or analog output channels on a  Data Acquisition device. A major consideration for testing NMOS transistors in the saturation region is that they can operate at very low values of iD. Acquiring the curves in Figure 3 at very low current values requires the ability to vary the value of VGS in very small increments. Using a resistor network, as shown in Figure 4, you can derive a VGS from the two voltage sources and decrease the step sizes to 10μV or less. You can use a single analog output channel for VDS because it does not have to be as precise as VGS.


Figure 4: PXI Setup for NMOS Transistor Characterization.


Using the configuration shown in Figure 4, VGS can be calculated by the following formula:

VGS = VAO 1 + (R2/R1+R2)*(VAO 0 – VAO 1)

Given R1 >> R2: The voltage at AO 0 will be a fine tune and AO 1 will be a coarse adjustment for VGS

Because we can operate the NMOS transistor at very low saturation levels, a high resolution measurement device, such as the PXIe-4081 Digital Multimeter (DMM), is required to measure iD. The PXIe-4081 DMM delivers 1 pA (10-12) resolution in the 1μA measurement range, which is ideal for acquiring low levels of iD

One common concern when measuring current at extremely low levels is the environmental noise on the system. Using shielded cables, shielded enclosures, and grounding devices appropriately is crucial for reducing noise in the measurement system. Another technique to reduce noise is to connect the High terminal of the DMM to the highest impedance source. In this case (Figure 4) the transistor’s impedance is greater than that of the M-Series analog output channel. Because the connection scheme causes current to flow from the Low to the High terminal of the DMM, we simply negate the current values acquired by the PXIe-4081 programmatically.

 

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3. Software Solution for Acquiring Characteristic Curves


With a test platform in place, LabVIEW now controls the system by adjusting drain and gate voltages, acquiring iD, and displaying the characteristic curves. The NI-DMM driver configures the PXI-4081 DMM to accurately acquire iD along the entire range of the characteristic curve. As the value of iD exponentially increases, the range of the DMM is adjusted on the fly in order to maintain maximum resolution for all current levels. The figures below show the two characteristic curves acquired and analyzed using LabVIEW.


Figure 5: iD vs. VDS with LabVIEW


Figure 6: iD vs. VGS with LabVIEW

 

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4. Example Program


The example attached was created specifically for NMOS testing with the setup shown in Figure 4. It demonstrates all of the abilities described in this white paper.
  

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5. Other Applications


NMOS transistor characterization is one example that demonstrates National Instruments capabilities with low current applications. With the ability to measure current with an accuracy of 1pA, the PXIe-4081 DMM is ideal for applications such as testing and measuring leakage currents and IC characterization. The versatile architecture of the PXIe-4081 DMM allows it to sweep between current ranges of 1pA up to 3A while providing flexible resolution up to 7½ digits and sampling rates up to 1.8MS/s in isolated digitizer mode. Combining the hardware capabilities with LabVIEW gives users an open ended tool for acquiring, analyzing, and presenting data as illustrated by this document. For more information about the NI 4081 DMM, please use the link below.

 

See Also:
PXIe-4081 DMM Product Page


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