1. NMOS Transistor Basics
Figure 1: NMOS Transistor
NMOS transistors consist of three terminals: gate, drain, source, and body. The source and body are both grounded and the device will operate, or in other words, a drain current (iD) will be induced based on voltages applied at the gate (VGS) and drain (VDS) of the transistor. Every NMOS transistor contains a threshold voltage (Vt) which is constant and unique for each transistor. In order for the transistor to operate, VGS must be greater than Vt. Once this condition has been met, the resulting drain current can be controlled by the voltages supplied at the gate and the drain. The relationship between VGS, VDS, and iD is described by three regions of operation:
1. Cut-off Region: In this region no channel exists (iD = 0) for all values of VD. (VGS < Vt)
2. Ohmic/Triode Region:
The NMOS transistor is active and not “pinched off.” This means the value of VDS affects the value of iD (VGS > Vt and VDS ≤ VGS – Vt). Figure 2 shows the relationship between VGS, VDS, and iD in this region. Notice the linear relationship between iD and VDS. In this region, iD obeys Ohms Law as the NMOS transistor responds as a voltage controlled resistor.
Figure 2: iD vs. VDS (Ohmic/Triode Region)
3. Active/Saturation Region: The channel is “pinched off” because increases in VD have no affect on iD (VGS > Vt and VDS > VGS – Vt). In the saturation region, the amount of drain current is directly related to the values of VGS > Vt.
Figure 3: iD vs. VDS (left) and iD vs. VGS (right)
The two characteristic curves provide important information for engineers implementing NMOS transistors into their system by illustrating whether a particular unit will pass or fail within a certain region of operation. Figure 3 depicts the transition from the triode region into the saturation region given discrete values of VGS and shows the response of iD to changes in VGS while the NMOS transistor is in the saturation region. With enough precision, these curves can be analyzed with an resolution of 1pA.
2. Hardware Setup for Testing NMOS
Testing the NMOS and acquiring the characteristic curves require a voltage source for both VGS and VD, and a device to measure iD. For the programmable voltage sources, consider using a Data Acquisition device which contains 4 analog output channels. A major consideration for testing NMOS transistors in the saturation region is that they can operate at very low values of iD. Acquiring the curves in Figure 3 at very low current values requires the ability to vary the value of VGS in very small increments. The M-Series’ absolute accuracy for analog output is 260μV at the lowest range setting. Using a resistor network, as shown in Figure 4, you can derive a VGS from the two voltage sources and decrease the step sizes to 10μV or less. You can use a single analog output channel for VDS because it does not have to be as precise as VGS.
Figure 4: PXI Setup for NMOS Transistor Characterization.
Using the configuration shown in Figure 4, VGS can be calculated by the following formula:
VGS = VAO 1 + (R2/R1+R2)*(VAO 0 – VAO 1)
Given R1 >> R2: The voltage at AO 0 will be a fine tune and AO 1 will be a coarse adjustment for VGS
Because we can operate the NMOS transistor at very low saturation levels, a high resolution measurement device, such as the PXI-4071 FlexDMM, is required to measure iD. The PXI-4071 FlexDMM delivers 1 pA (10-12) resolution in the 1μA measurement range, which is ideal for acquiring low levels of iD. One concern when measuring current at extremely low levels is environmental noise on the system. Using shielded cables, shielded enclosures, and grounding devices appropriately is crucial for reducing noise to minimal levels. Another technique to reduce noise is to connect the High terminal of the DMM to the highest impedance source. In this case (Figure 4) the transistor’s impedance is greater than that of the M-Series analog output channel. Because the connection scheme causes current to flow from the Low to the High terminal of the DMM, we simply negate the current values acquired by the PXI-4071 programmatically.
3. Software Solution for Acquiring Characteristic Curves
With a test platform in place, LabVIEW now controls the system by adjusting drain and gate voltages, acquiring iD, and displaying the characteristic curves. The NI-DMM driver configures the PXI-4071 FlexDMM to accurately acquire iD along the entire range of the characteristic curve. As the value of iD exponentially increases, the range of the DMM is adjusted on the fly in order to maintain maximum resolution for all current levels. The figures below show the two characteristic curves acquired and analyzed using LabVIEW.
Figure 5: iD vs. VDS with LabVIEW
Figure 6: iD vs. VGS with LabVIEW
4. Example Program
5. Other Applications
NMOS transistor characterization is one example that demonstrates National Instruments capabilities with low current applications. With the ability to measure current with an accuracy of 1pA, the PXI-4071 FlexDMM is ideal for applications such as testing and measuring leakage currents and IC characterization. The versatile architecture of the PXI-4071 FlexDMM allows it to sweep between current ranges of 1pA up to 3A while providing flexible resolution up to 6 1/2 digits and sampling rates up to 1.8MS/s. Combining the hardware capabilities with LabVIEW gives users an open ended tool for acquiring, analyzing, and presenting data as illustrated by this document. For more information about the NI 4071 FlexDMM, please use the link below.
NI 4071 FlexDMM Product Page