M Series Synchronization with LabVIEW and NI-DAQmx

Publish Date: Mar 12, 2012 | 39 Ratings | 4.03 out of 5 |  PDF

Table of Contents

  1. Introduction
  2. Overview of M Series Clock Derivation
  3. Register Device in the Measurement & Automation Explorer (MAX)
  4. Multifunction Synchronization
  5. Multidevice Synchronization

 The National Instruments Getting Started with NI-DAQmx Series is aimed at helping you learn NI-DAQmx programming fundamentals. Through video and text tutorials, this series will take you from verifying the operation of your device in Measurement & Automation Explorer (MAX) to programming data acquisition applications using NI LabVIEW. It is intended for both the beginner who wants to learn how to use DAQ Assistant, as well as the experienced user who wishes to take advantage of advanced NI-DAQmx functionality.

1. Introduction

Many applications require precise control of timing and the ability to synchronize multiple operations. National Instruments M Series data acquisition devices provide excellent tools for synchronization and are well suited for these applications. This paper will present and analyze the recommended methods for multifunction and multidevice M Series synchronization with NI-DAQmx measurement services and LabVIEW, which is the graphical development environment for creating flexible and scalable test, measurement, and control applications rapidly and at minimal cost. With LabVIEW, engineers and scientists interface with real-world signals, analyze data for meaningful information, and share results and applications. Additionally, this paper will present the recommended method to synchronize E Series and M Series devices.

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2. Overview of M Series Clock Derivation


Before discussing synchronization, it is helpful to first understand the different clocks present in M Series devices. The NI-STC 2 timing and controller ASIC on M Series devices generates several timebases by dividing down an 80 MHz timebase. This 80 MHz timebase is derived in one of two ways – either from the 80 MHz onboard oscillator or from the phase-lock-loop (PLL) circuit , as shown in Figure 1 below. When the reference clock for the PLL is shared among devices, the 80 MHz timebase produced from the PLL will be synchronized among those devices. Thus, all the clocks derived from that 80 MHz timebase or the resulting 20 MHz timebase will also be synchronized. Due to the way signals are divided, the 100 kHz timebase will not be in phase with the input to the PLL. These timebase signals are used internally as clock sources for the analog input, analog output, and counter/timers subsystems of the device. For example, the analog input subsystem will divide down one of these timebases to create its AI Sample Clock. From this 80 MHz onboard oscillator, each M Series device also generates its own 10 MHz reference clock, which can be used for synchronization in a multidevice system.


Figure 1 Clock Routing Circuitry of an M Series Device


Sample clocks for analog operations on M Series devices are typically obtained by dividing down either the 20 MHz or 100 kHz internal timebase. The counter/timers are the only subsystem that can directly use the 80 MHz timebase. It is also possible to source other external and internal signals such as the PXI_STAR trigger, analog comparison event, or signals from PFI lines or the RTSI bus. For more information about AI and AO sample clock derivation, read the timing signal sections of the M Series User Manual .

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3. Register Device in the Measurement & Automation Explorer (MAX)

Setting up the hardware to allow synchronization is accomplished through the Measurement & Automation Explorer (MAX), which is a program that provides access to your National Instruments devices so you can configure your hardware and software accordingly. The steps necessary for configuring your hardware are different depending on whether the device is a PCI board or a PXI module. For PCI boards, a RTSI cable, that should by physically connected to all of the boards between which you want to route signals, must be virtually created and registered in MAX. Once the RTSI cable is created, the boards will need to be added to the RTSI cable, and the NI-DAQmx driver can route signals between devices accordingly. This feature is discussed in more detail in the Timing and Synchronization Features of NI-DAQmx tutorial. For PXI modules, the idea is the same, but the only thing that needs to be done is to identify the PXI chassis. There are no cables required for PXI modules because the equivalent of the RTSI bus is contained in the backplane of the PXI chassis. This too is discussed in the above mentioned tutorial.

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4. Multifunction Synchronization


Synchronization can be broken down into two major types: multifunction and multidevice. Multifunction synchronization includes operations that occur simultaneously on a single device. In other words, operations such as simultaneous analog input/analog output and simultaneous digital input/analog output fall under the heading multifunction synchronization. For the purposes of this paper, multifunction synchronization is divided into two categories: sharing a start trigger and sharing a sample clock. Multidevice synchronization refers to synchronizing operations across multiple devices in your system and is discussed later in this paper.

Shared Start Trigger
When performing most multifunction synchronization, only a start trigger is needed. This is because the two operations derive their sample clocks from a common timebase internal to the device. In the LabVIEW example below that shows how to perform simultaneous analog voltage measurement and voltage generation, both analog operations derive their individual AI and AO sample clocks from the same internal 20 MHz or 100 kHz timebase inherent to the device. The operations will remain synchronous if given an identical rate. If the sample clock rates are set to different frequencies, the operations will be simultaneously started but not fully synchronized. Also note that the two operations can be configured to acquire different amounts of data.



Figure 2 Simultaneous Start Example


In the above example, there are two processes that occur concurrently. The top process controls the analog input and the bottom process controls the analog output. Each step, indicated by a number at the bottom of the figure, is described below.

  1. In step 1, both the analog input and analog output channels are created. The initialization procedure acquires the physical channel and the type of operation to perform (i.e. analog input on channel ai0 of Dev1).
  2. Step 2 is very important to the synchronization process. Using the DAQmx Timing VI, the two sample clocks are defined for finite acquisitions. Both this and the sample rate are determined by the specific application. For processes that start simultaneously but occur at different intervals, the sample clocks are assigned different rates. For operations in which the two processes are to occur in both a simultaneous and correlated manner, the samples clocks are assigned the same rate.
  3. In step 3, a Get Terminal Name with Device Prefix VI (C:\Program Files\National Instruments\LabVIEW 7.1\examples\DAQmx\_Utility\_Utility.llb) creates the terminal name to be used by the DAQmx Trigger VI. The purpose of this VI is for greater generalization in programming. Specifically this VI extracts the device name and appends the input string as a terminal name. Also in step 3, the DAQmx Trigger VI causes the analog output operation to wait for a digital trigger to begin executing. The source of this trigger is defined as the analog input start trigger, as derived by the Get Terminal Name with Device Prefix VI. The ai/StartTrigger signal is generated automatically as soon as the analog input operation is started. This trigger is then used to simultaneously start the analog output operation.
  4. Using the DAQmx Write VI, the analog output buffer is loaded with data.
  5. At this point, the analog output operation is started with the DAQmx Start Task VI. However, it has been configured to wait for a trigger and will not execute until the ai/StartTrigger goes high. Immediately thereafter, the other DAQmx Start Task VI is used to begin the analog input operation and sends the trigger signal. The sequence structure ensures that the analog output process has been started and is waiting for a digital trigger before the analog input process sends the trigger.
  6. The DAQmx Read VI will read a finite number of samples.
  7. Finally, the DAQmx Is Task Done VI checks that the program has completed writing the analog output, and the tasks are cleared. The error clusters are merged and passed to a simple error handler.


Shared Sample Clock
The second form of single device, multifunction synchronization involves sharing a sample clock. Sharing the sample clock is probably the most common way to synchronize single device operations because it ensures that the operations start at the same time and proceed at the same rate. The simultaneous analog voltage measurement and voltage generation example above could have also been achieved by sharing the AI or AO Sample clock between both subsystems. A great example of when to use this method is when you want to correlate digital and analog waveform operations on an M Series device.

Unlike E Series devices, the M Series device can be used for hardware-timed digital operations. However, the digital subsystem of an M Series device does not have the ability to divide down one of the timebases to create an internal clock for digital input or output operations. An external signal or one of the many internal signals from another subsystem must be provided as the digital sample clock. For example, one can synchronize digital and analog operations by sharing the AI or AO Sample Clock as the source of your DI or DO Sample clock. To sample a digital signal independent of an AI, or AO operation, a counter or an external signal can be configured to generate the desired DI Sample Clock.

The example below demonstrates how to synchronize an analog input operation with a digital input operation. The digital acquisition will not begin until the analog input operation has started and the AI Sample Clock is generated.




Figure 3 Shared Sample Clock and Simultaneous Start


In the example shown above, the digital input circuitry uses a shared sample clock to synchronize analog and digital input.

  1. In step 1, the analog input and digital input channels are created. The initialization procedure acquires the basic information needed to describe the operation.
  2. Using two DAQmx Timing VIs, the sample modes are defined as continuous or finite acquisitions. The sample mode is determined by the specific application. Because the sample clock is being shared, the two operations should use the same sample rate. In this example, the rate is 1 kHz. Additionally, the DAQmx Timing VI should set the digital timing source to be the analog input sample clock. This causes the digital input circuitry to latch the digital lines at the same time that the analog channels are sampled.
  3. At this point, the analog input and digital input operations are started with the DAQmx Start Task VI. The sequence structure ensures that the digital input process has been started and is waiting for the analog input to start. As stated before, the digital task does not have a defined trigger; however the digital task will not start until the analog input sample clock is available. The analog input sample clock will be available when the analog input task is started.
  4. The DAQmx Read VIs will each read a finite number of samples.
  5. Finally, the tasks are cleared.
  6. The error clusters are merged and passed to a simple error handler.

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5. Multidevice Synchronization

PCI Synchronization Using the Reference Clock
The RTSI bus offers the ability to share signals between independent devices in the system. Traditionally, synchronizing data acquisition devices required sharing a common timebase clock source among the devices. M Series devices have an internal timebase of 80 MHz, which is too high a frequency to pass accurately to other devices through the RTSI bus. Typically, 10 MHz is a more stable clock frequency to route between devices and is used as a standard for synchronization in PXI systems with the 10 MHz PXI clock built into the backplane of the chassis. Therefore, M Series devices generate a 10 MHz reference clock to be used for synchronization purposes by dividing down their 80 MHz onboard oscillator. To synchronize acquisitions or generations across several PCI M Series boards, one board acts as the master and exports its 10 MHz reference clock to all of the other slave boards. The NI-STC 2 ASIC on each M Series has PLL circuitry that compares an external reference clock to its built in voltage-controlled crystal oscillator clock (VCXO) to output a clock that is synchronized to this reference. Thus each device in the system can input a 10 MHz reference clock and synchronize its own 80 MHz and 20 MHz timebases to it. With this technology, all devices are synchronized to the same 10 MHz master clock, but can use their individual faster 80 and 20 MHz timebases generated onboard. Note that due to the way signals are divided down, the 100 kHz timebase will not be in phase with the input to the PLL. Refer to Figure 1 for an overview of the timebase routing for M Series devices. Figure 4 shows how the PLL and a reference clock are used to synchronize two high-speed clocks, 100 MHz in this case.



Figure 4 Concept of Synchronization Using a Reference Clock




When routing its 10 MHz reference clock out for other devices to synchronize to, the master device can set the source of its reference clock to "OnboardClock". This option will take the 10 MHz reference clock of the master device, which has been routed out to RTSI, back to the source of its own PLL. The master device then sees the same delays that the slave devices phase locking to the 10 MHz reference clock over RTSI will see. Note that by default, the source of an M Series reference clock is set to "none". This will cause the M Series device to use its onboard oscillator as the source of its timebases.

Figure 5 shows an example of multidevice synchronization of two M Series boards using the reference clock of the master device. The labels on the figure correspond to important parts of the program and a description for each is given below.



Figure 5 PCI Synchronization with 10 MHz Reference Clock

  1. In Step 1, virtual channels are created. Each one of the virtual channels in question here is used to acquire from an analog voltage signal. Notice that they are from independent devices – M Series Master and M Series Slave.
  2. In this step, the timing information is entered. Both channels are set for finite acquisition of 1000 samples/channel at a rate of 1000 samples/s. The source of each sample clock is left to the default value, which is just the internal analog input sample clock that will be derived from dividing down one of the internal timebases of the device.
  3. The reference clock of the master device is set to OnboardClock. This will cause the master device to output its 10 MHz reference clock to RTSI and back into the source of its own PLL to synchronize its PLL oscillator with the same 10 MHz reference clock that the slave devices will use. The source of the master reference clock is then queried and used to set the source of the slave reference clock, which causes the 10 MHz reference clock to automatically be routed through RTSI to the input of the slave device PLL as a reference to phase lock its timebases to. Using this process, the two devices can each use its own timebases, but then be synchronized indirectly through the reference clock. By choosing OnboardClock, the master incurs the same delay encountered by the slave receiving the signal through RTSI, making the whole synchronization process more accurate.
  4. As with the simultaneous start example, the Get Terminal Name with Device Prefix VI is used to programmatically extract the Start Trigger signal of the master device and route it to be used to start the slave device. This step is the second phase of the synchronization – making sure that they start at the same time.
  5. The task from the slave is started first, but will wait to receive a trigger signal from the master Start Trigger that was routed in the previous step. When the master is started, the Start Trigger signal is generated and triggers both tasks at the same time. The sequence structure is used to ensure that the slave is started before the master and to avoid race conditions.
  6. At this step, the samples are read by both tasks. Each task will provide 1000 samples and display them on a waveform graph.
  7. After the acquisition is done, the tasks are cleaned in this step. This step ensures that the resource is freed and can be used by another task.
  8. This last step handles the errors that might have occurred during the acquisitions. Error clusters from both tasks are merged into one error cluster and wired into the error handler.


PXI Synchronization Using the Reference Clock
PXI and PCI synchronization are very similar in the sense that they use the same reference clock principle. In a PXI system, a common 10 MHz reference clock for synchronization of multiple modules is already built into the backplane with the PXI_CLK10 signal. To synchronize multiple M Series modules in a PXI system, each one of the M Series modules should use the PXI_CLK10 as its reference clock, which will cause the timebases on all boards to be synchronized with one another. If one master device sends out a start trigger to the other devices and all of their sample clocks are set to the same rate, the acquisitions will be synchronized. Figure 6 shows the block diagram representing M Series PXI synchronization.



Figure 6 PXI Synchronization with PXI_CLK10


  1. In Step 1, virtual channels are created. Each of the virtual channels is used to acquire from an analog voltage signal. Notice that they are from independent devices – M Series Master and M Series Slave.
  2. In this step, the timing information is entered. Both channels are set for finite acquisition of 1000 samples/channel at a rate of 1000 samples/s. The source of each sample clock is left to the default value, which is just the internal analog input sample clock that will be derived from dividing down one of the internal timebases on the device.
  3. Next, the reference clock source of each device is set to PXI_CLK10, which is the same principle as in the PCI reference clock above. The only difference is the fact that each PXI module synchronizes its internal timebases to the PXI backplane 10 MHz clock.
  4. As with the PCI reference clock example, the Get Terminal Name with Device Prefix VI is used to programmatically extract the Start Trigger signal of the master device and route it to be used to start the slave device. This step is the second phase of the synchronization – making sure that they start at the same time.
  5. The task from the slave is started first, but has to wait to receive a trigger signal from the master Start Trigger that was routed in the previous step. When the master is started, the Start Trigger signal is generated to trigger the slaves. The sequence structure is used to ensure that the slave is started before the master and to avoid race conditions.
  6. At this step, the samples are read by both tasks. Each task will provide 1000 samples and display them on a waveform graph.
  7. After the acquisition is done, the tasks are cleaned in this step. This step ensures that the resource is freed and can be used by another task.
  8. This last step handles the errors that might have occurred during the acquisitions. Error clusters from both tasks are merged into one error cluster and wired into the error handler.


An Alternative Method ¬¬– Synchronization by Sharing a Sample Clock
Other data acquisition devices, such as E Series, do not offer a reference clock for synchronization purposes. A common way to synchronize these devices, which will also work for M Series devices, is to share a common sample clock across all devices in the acquisition. This can be done by routing the master sample clock over RTSI to be used as the sample clock for all slave devices. There are slight disadvantages with using this method. One is that small propagation delays are introduced between the master and slave by routing the sample clock over RTSI that do not exist when using a reference clock for synchronization. The second is that although a common AI Sample Clock is shared between all boards, the AI Convert Clocks that actually cause the A/D conversions on each channel for devices with multiplexed architectures (such as E Series and M Series) are still generated from each onboard oscillator, which will not be synchronized to each other. However, these errors are small and negligible for most E and M Series applications.

The example shown in Figure 7 demonstrates how to synchronize an acquisition between two M series devices by sharing a sample clock. With NI-DAQmx, the master sample clock will automatically be routed to the slave over RTSI bus or the PXI trigger lines by setting the source of the slave sample clock to be the master sample clock. Below are the descriptions of each of the steps labeled by the numbers on the figure.



Figure 7 Synchronization of Two M Series Devices Using the Sample Clock


  1. In step 1, virtual channels are created. Each of the virtual channels is used to acquire an analog voltage signal. Notice that they are from independent devices – M Series Master and M Series Slave.
  2. In this step, the timing information is entered. Both channels are set for finite acquisition of 1000 samples/channel at a rate of 1000 samples/s. This time, the SampleClock source of the slave is chosen to be the AI Sample Clock of the master device. NI-DAQmx will automatically make the necessary route to the slave over RTSI. The source of the master SampleClock is left to the default, which will be the internal analog input SampleClock.
  3. As it was done previously, the Get Terminal Name with Device Prefix is used to programmatically extract the Start Trigger signal of the master device and route it to be used to start the slave device. This step is the second phase of the synchronization – making sure that they start at the same time.
  4. The task from the slave is started first, but has to wait to receive a trigger signal from the master Start Trigger that was routed in the previous step. When the master is started, the Start Trigger signal is generated and triggers both tasks at the same time. The sequence structure is used to ensure that the slave is started before the master and to avoid race conditions.
  5. At this step, the samples are read by both tasks. Each task will provide 1000 samples and display them on a waveform graph.
  6. After the acquisition is done, the tasks are cleaned in this step. This step ensures that the resource is freed and can be used by another task.


Special case – E Series and M Series Synchronization
E Series devices have been leading the market for data acquisition products for many years, and with the introduction of the new NI M Series devices, we feel strongly that NI multifunction data acquisition devices will continue to lead the market. As a result, it is important that current E Series users be able to use both E and M Series devices simultaneously. For this reason, this section presents the recommended method for synchronizing E Series and M Series devices.

E Series and M Series devices employ slightly different techniques for synchronization. To synchronize operations across multiple E Series devices, one device will export its 20 MHz master timebase to be used as the master timebase for the other devices. Although an E Series device can input a slower signal, such as 10 MHz, for its master timebase it cannot multiply that timebase up to re-create a 20 MHz timebase. Therefore, the resolution of the internal sample clocks that the E Series device could create by dividing down this external master timebase would be decreased. M Series devices cannot directly route out their internal 20 MHz timebase over the RTSI bus. M Series devices are able to directly route out only their 10 MHz reference clock. Therefore, the E Series device should be used as the master device when synchronizing an E Series and an M Series device. In this case, the E Series device can route out its 20 MHz master timebase to be used as the reference clock source for the M Series slave. The timebase on the M Series device would then be in phase with the 20 MHz master timebase of the E Series device.

Another behavior difference that must taken into account when synchronizing E and M Series devices is the difference in the default sample clock delay. The sample clock delay is the delay between when the AI Sample Clock occurs and when the first AI Convert Clock pulse for that scan occurs. With E Series, this default delay is 2 ticks of the master timebase, which is the minimum value allowed. With M Series, the default delay is 3 ticks of the timebase being used. Therefore, to more precisely synchronize an E Series device with an M Series device, change the E Series device to have a sample clock delay of 3 ticks. Figure 8 below demonstrates this behavior.


Figure 8 Default DelayFromSampleClk of E Series and M Series


Figure 9 is an example on how to synchronize an acquisition between an E Series and an M Series device.


Figure 9 E Series-M Series Synchronization
  1. In step 1, both the E Series and M Series analog input channels are created. The initialization procedure acquires the basic information needed to describe the operation.
  2. Using the DAQmx Timing VI, the two sample clocks are defined for continuous or finite acquisitions. Both devices are set to use the same sample rate. The clock source is not defined by the DAQmx Timing VI.
  3. Using two property nodes, the master timebase source and rate from the E Series device are routed to the M Series reference clock source and rate. By doing this, the M Series device will phase lock its internal timebases to the 20 MHz master timebase from the E Series device.
  4. In addition, the DelayFromSampleClk of the E Series device has to match that of the M Series device. This delay represents the number of timebase ticks after the sample clock and before the first convert clock (see Figure 8).
  5. In step 5, the Get Terminal Name with Device Prefix VI extracts the device name and appends the input string as a terminal name. The DAQmx Trigger VI causes the M Series analog input operation to wait for a digital trigger to begin executing. The source of this trigger is defined as the analog input start trigger from the E Series device. As a result, the E Series and M Series analog input operations will begin simultaneously.
  6. At this point, the two analog input operations have been started with the DAQmx Start Task VI. The M Series analog input operation has been configured to wait for a start trigger and will not execute until the E Series device begins data acquisition. The sequence structure ensures that the M Series analog input process has been started and is waiting for a digital trigger. The two DAQmx Read VIs will read a finite number of samples.
  7. In this last step, the tasks are cleaned and the errors are handled. Both error clusters (from both tasks) are merged and wired into the error handler.

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