Field-programmable gate array (FPGA) technology provides the reliability of dedicated hardware circuitry, true parallel execution, and lightning-fast closed-loop control performance. This application note provides answers to frequently asked questions (FAQs) regarding the use of reconfigurable FPGA-based hardware targets for closed-loop control applications.
Figure 1. NI CompactRIO is a small, rugged FPGA-based control system
2. What is a field-programmable gate array (FPGA)?
An FPGA is a device that contains a matrix of reconfigurable gate array logic circuitry. When an FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application. Unlike processors, FPGAs use dedicated hardware for processing logic and do not have an operating system. FPGAs are truly parallel in nature so different processing operations do not have to compete for the same resources. As a result, the performance of one part of the application is not affected when additional processing is added. Also, multiple control loops can run on a single FPGA device at different rates. FPGA-based control systems can enforce critical interlock logic and can be designed to prevent I/O forcing by an operator. However, unlike hard-wired printed circuit board (PCB) designs, which have fixed hardware resources, FPGA-based systems can literally rewire their internal circuitry to allow reconfiguration after the control system is deployed to the field. FPGA devices deliver the performance and reliability of dedicated hardware circuitry.
A single FPGA can replace thousands of discrete components by incorporating millions of logic gates in a single integrated circuit (IC) chip. The internal resources of an FPGA chip consist of a matrix of configurable logic blocks (CLBs) surrounded by a periphery of I/O blocks. Signals are routed within the FPGA matrix by programmable interconnect switches and wire routes.
Figure 2. Looking inside an FPGA chip
3. How do FPGA-based control systems compare to processor-based systems?
Like processor-based control systems, FPGAs have been used to implement all types of industrial control systems, including analog process control, discrete logic, and batch or state-machine-based control systems. However, FPGA-based control systems differ from processor-based systems in significant ways.
When you compile your control application for an FPGA device, the result is a highly optimized silicon implementation that provides true parallel processing with the performance and reliability benefits of dedicated hardware circuitry. Because there is no operating system on the FPGA chip, the code is implemented in a way that ensures maximum performance and reliability.
In addition to offering high reliability, FPGA devices can perform deterministic closed-loop control at extremely fast loop rates. In most FPGA-based control applications, speed is limited by the sensors, actuators, and I/O modules rather than the processing performance of the FPGA. For example, the proportional integral derivative (PID) control algorithm that is included with the LabVIEW FPGA Module executes in just 300 nanoseconds (0.000000300 seconds). PID control is commonly used for regulating analog process values such as pressure, temperature, force, displacement, fluid flow, or electrical current.
Figure 3. Performing PID control in LabVIEW FPGA
FPGA-based control systems offer deterministic closed control performance at rates exceeding 1 MHz. In fact, many algorithms can be executed in a single cycle of the FPGA clock (40 MHz). Processing is done in parallel so multirate control systems are easy to implement. Because control logic runs in dedicated hardware subsystems on the FPGA, applications do not slow down when additional processing is added. In many cases, a software-defined gate array in FPGA hardware can be used to replace a costly and time-consuming custom printed circuit board (PCB) layout.
FPGAs can digitally process signals at very high speeds and are often used to reconfigure the I/O module functionality. For example, a digital input module can be used to simply read the true/false state of each digital line. Alternately, the same FPGA can be reconfigured to perform processing on the digital signals and measure pulse-width, perform digital filtering, or even measure position and velocity from a Quadrature encoder sensor.
FPGA-based systems often incorporate motion control and motor drive commutation in a single FPGA-based motion control system. By contrast, microprocessor-based systems typically offload the motor drive commutation to separate hardware because motor current or torque control requires fast loops rates (commonly 20 kHz) and precise timing of the gate drive commutation signals.
Figure 4. Microprocessor-based control (left) versus FPGA-based control (right)
4. How do I program my control application using the LabVIEW FPGA Module?
With the LabVIEW FPGA Module, you can use high-level graphical dataflow programming to create a highly optimized gate array implementation of your analog or digital control logic. You can use normal LabVIEW programming techniques to develop your FPGA application. When you target FPGA hardware such as a CompactRIO chassis or R Series intelligent DAQ device, the LabVIEW programming palette is simplified to contain only the functions that are designed to work on FPGAs. The primary programming difference compared to traditional LabVIEW is that FPGA devices use integer math rather than floating-point math. Also, there is no notion of multithreading or priorities because each loop executes in independent dedicated hardware and does not have share resources — in effect, each loop executes in parallel at “time critical” priority.
The LabVIEW FPGA palette contains extensive intellectual property (IP) libraries. The table below lists some of the key function blocks for developing FPGA-based control systems.
|Category||Key Functions for Control||Common Control Applications|
|Programming Structures||For Loop, While Loop, Case Structure, Feedback Node, Sequence Structure, Single Cycle Timed Loop, Shift Register, HDL Interface Node||Analog process control loops, state-machines, batch control, sequential function charts, event response, repeated execution, signal latching, subroutines, sequencing, system state control (power up, shut down, watchdog, fault, …)|
|Input/Output||Analog Input, Analog Output, Digital Input, Digital Output, Digital Port Input, Digital Port Output||Interfacing to digital I/O, voltage, current, temperature, load, pressure, strain, relay, 4-20 mA, H-bridge, CAN communication, wireless networking, and other signals|
|Analog Control||Discrete PID, Discrete Control Filter, Discrete Delay, Discrete Normalized Integrator, Initial Condition, Unit Delay, Zero-Order Hold, Backlash, Dead Zone, Friction, Memory Element, Quantizer, Rate Limiter, Relay, Saturation, Switch, Trigger, Linear Interpolation, Sine Generator, Look-Up Table 1D||Analog control algorithms, filtering of noisy signals, limiting input/output signals, scaling nonlinear sensor signals to engineering unit proportional values, function generation, sine, cosine, log, exponential, gain scheduling, ramp/soak|
|Discrete Logic||And, And Array Elements, Boolean Array To Number, Boolean To (0,1), Compound Arithmetic, Exclusive Or, Implies, Not, Not And, Not Exclusive Or, Not Or, Number To Boolean Array, Or, Or Array Elements, Boolean Crossing||Digital control, digital logic, Boolean logic, relay ladder logic, sequence of events, state transitions, control of 2-state and 3-state discrete devices, edge detection|
|Comparison Functions||Equal?, Equal To 0?, Greater?, Greater Or Equal?, Greater Or Equal To 0?, Greater Than 0?, Less?, Less Or Equal?, Less Or Equal To 0?, Less Than 0?, Not Equal?, Not Equal To 0?, Select, Max & Min, In Range and Coerce, Zero Crossing,||Alarming, triggering, event detection, peak detection, signal comparison, thresholding, change of state detection, signal selection (high, min, max), limit testing, selector/multiplexer, heating/cooling split range control|
|Math||Absolute Value, Add,
Compound Arithmetic, Decrement, Increment, Multiply, Negate, Quotient & Remainder, Scale By Power Of 2, Sign,
Subtract, Saturation Add, Saturation Multiply, Saturation Subtract, Join Numbers, Logical Shift, Rotate, Rotate Left With Carry, Rotate Right With Carry, Split Number, Swap Bytes, Swap Words
|Analog signal manipulation, summing, counter/timers, rate of change detection, electronic gearing/camming, accumulator, averaging, totalizer, digital signal processing|
|Data Transfer, Timing, Triggering and Synchronization||Global Variable, Local Variable, FIFO Read, FIFO Write, Memory Read, Memory Write, Interrupt, Loop Timer, Tick Count, Wait, Generate Occurrence, Set Occurrence, Wait On Occurrence, First Call?||Watchdogs, timers, accumulators, pulse width measurement/generation, timer on/off delay|
|NI SoftMotion Module||Motion ControlLoop PID (32-bit), Spline Engine (Interpolation)||Multiaxis coordinated motion control, trajectory generation, straight line moves, jogging, arc move, contouring, interpolation|
|Digital Filter Design Toolkit||Filter Design, Fixed-Point Tools, Code Generation||Digital filter design, convert floating-point to fixed-point, generate LabVIEW FPGA code|
Table 1. Key Functions for Control in LabVIEW FPGA
5. How does the LabVIEW compiler translate my graphical code into FPGA circuitry?
The LabVIEW FPGA module compiles your LabVIEW application to FPGA hardware using an automatic multistep process. Behind the scenes, your graphical code is translated to text-based VHDL code. Then industry standard Xilinx ISE compiler tools are invoked and the VHDL code is optimized, reduced, and synthesized into a hardware circuit realization of your LabVIEW design. This process also applies timing constraints to the design and tries to achieve an efficient use of FPGA resources (sometimes called “fabric”).
A great deal of optimization is performed during the FPGA compilation process to reduce digital logic and create an optimal implementation of the LabVIEW application. Then the design is synthesized into a highly optimized silicon implementation that provides true parallel processing capabilities with the performance and reliability of dedicated hardware.
The end result is a bit stream file that contains the gate array configuration information. When you run the application, the bit stream is loaded into the FPGA chip and used to reconfigure the gate array logic. The bit stream can also be loaded into nonvolatile Flash memory and loaded instantaneously when power is applied to the target. There is no operating system on the FPGA chip, however execution can be started and stopped using enable-chain logic that is built into the FPGA application.
Figure 5. LabVIEW FPGA Compilation Process
6. FPGAs are fast, but how do faster loop rates improve control system performance?
In general, the speed of the control system impacts its performance, stability, robustness and disturbance rejection characteristics. Faster control systems are typically more stable, easier to tune, and less susceptible to changing conditions and disturbances.
To provide stable and robust control, a control system must be able to measure the process variable and set an actuator output command within a fixed period of time. Systems (plants) that can change quickly require fast control systems to guarantee reliable performance within acceptable limits. As a rule, the control loop rate should be at least 10 times faster than the time constant of the system (plant). The time constant is a measure of the speed of the system.
For example, the current in a DC motor may change as fast as 1 amp per millisecond in response to a 24 V output from an H-bridge driver. To precisely control the motor current, the control system must sample the current quickly and make frequent adjustments to the actuator output.
Figure 6. Typical closed loop control system
7. What FPGA hardware targets are available from NI?
National Instruments offers a number of high-performance platforms for deploying your FPGA-based control applications. Several key platforms are introduced in this section. For a complete list of reconfigurable hardware targets from NI, visit ni.com/fpga-hardware.
The CompactRIO reconfigurable embedded system is a small modular system for industrial applications that require the highest level of ruggedness and reliability. CompactRIO is designed for harsh environments and offers a wide temperature range, high shock and vibration ratings, and an array of industrial certifications and ratings. CompactRIO is rated for marine environments, Class I, Division 2 rating for hazardous locations and offers up to 2,300 V of isolation. Like all FPGA targets from NI, CompactRIO uses the C Series industrial I/O modules for low-cost connectivity directly to industrial control sensors and actuators. In addition, there are many third-party vendors around the world that offer C Series I/O and communication modules. For a tutorial on performing control with CompactRIO, download the CompactRIO machine automation white paper.
Figure 7. CompactRIO Reconfigurable Embedded System
The NI R Series intelligent data acquisition (DAQ) devices are plug-in boards for PCI and PXI/CompactPCI buses with onboard FPGA hardware for user-defined signal processing and control. Up to 8 analog input, 8 analog output, and 160 digital I/O channels are built into the intelligent DAQ devices. You can also connect an expansion chassis to any digital port and add C Series industrial I/O modules. You can use R intelligent DAQ devices to define your own hardware functionality and offer limitless possibilities for timing, triggering, synchronization, digital signal processing, and control.
The PXI R Series intelligent DAQ system offers FPGA performance and reliability in the industry standard PXI form factor. In addition to the intelligent DAQ devices from NI, hundreds of non-reconfigurable plug-in boards are available from NI and other vendors around the world. The PXI system can be booted into Windows or the LabVIEW Real-Time operating system. C Series I/O modules provide signal conditioning and combine instrumentation grade accuracy with industrial features such as isolation or high current drive capability. The R Series expansion chassis is used to connect C Series modules to intelligent DAQ devices. For more information, see the online application notes explaining the R Series intelligent DAQ devices.
Figure 8. PXI R Series Intelligent DAQ System
The PCI R Series intelligent DAQ system lets you to add FPGA-based control capabilities to any desktop, industrial PC, or single-board computer (SBC) containing a PCI slot. Like all NI FPGA targets, the intelligent DAQ devices can load their bit stream instantly at power up from nonvolatile Flash storage located on the plug-in board. The NI-RIO driver interface is included with the R Series devices at no extra charge and no run-time deployment license fees are required. Read more.
Figure 9. PCI R Series Intelligent DAQ System
The NI Compact Vision System is a rugged stand-alone platform for industrial machine vision and I/O applications such as robotics, automated test, and automated inspection. All Compact Vision Systems contain a user-programmable FPGA for implementing custom triggers, counters, pulse-width modulation (PWM), motion, and other digital control operations. NI Compact Vision Systems use IEEE 1394 technology for interfacing to more than 300 compatible cameras.
Figure 10. NI Compact Vision System
To learn more about programmable automation controller (PAC) hardware technology from NI, visit ni.com/embeddedsystems.
8. What closed loop control performance can I achieve?
In most cases, the computational performance of the FPGA is so fast that the control loop rate is limited only by the sensors, actuators, and I/O modules. This is a stark contrast to traditional control systems, where the processing performance was typically the limiting factor.
For example, using R Series intelligent DAQ devices, the input/output and control logic calculations for discrete control applications can all be implemented at a 20 MHz control loop rate using the 5 V TTL digital I/O lines on the boards. These digital lines can be accessed from within a LabVIEW single-cycle timed loop executing at a 25 nanoseconds rate. Significant amounts of control logic can usually be included in a single-cycle timed loop.
For 24 V discrete logic control applications using high-current C Series digital I/O modules, the loop rate is limited to the update rate of the modules. For example, the NI 9423 digital input and NI 9474 digital output modules both have 1 microsecond update rates, resulting in a maximum 24 V discrete control performance of 500 kHz.
In analog process control applications, the control loop rate is also limited by the update rate of the I/O modules. The NI 9215 analog input and NI 9263 analog output modules offer 16-bit resolution and simultaneous sampling capabilities at 10 microsecond update rates. This results in a closed loop analog process control performance of 50 kHz.
Figure 11. The loop cycle time (T) is the time taken to execute one cycle of a control loop
9. How much jitter can I expect in my FPGA-based control loops?
A common gauge of control system performance and robustness is jitter, which is a measure of the variation of the actual loop cycle time from the desired loop cycle time. In general-purpose operating systems such as Windows, the jitter is unbounded so closed-loop control system stability cannot be guaranteed. Processor-based control systems with real-time operating systems are commonly able to guarantee control loop jitter of less than 100 microseconds.
In FPGA-based applications, the control loop does not need to share hardware resources with other tasks and control loops can be precisely timed using the FPGA clock. The jitter for FPGA-based control loops depends on the accuracy of the FPGA clock source. In the case of the NI cRIO-910x reconfigurable chassis, the FPGA clock jitter is only 250 picoseconds (0.000000000250 seconds) when using a 40 MHz FPGA clock rate.
Figure 12. To guarantee stability, control loop jitter must be bounded
10. Can I create my own custom I/O modules?
Yes, NI offers a module development kit (MDK), you can use to develop custom C Series modules and connect them to a reconfigurable FPGA. The kit provides license rights, design guidelines, and access to the generic I/O module node for creating an interface to your custom module-circuitry.
In addition National Instruments provides board-level design software with NI Multisim and Ultiboard. Multisim provides powerful, easy-to-use schematic capture and simulation software, which is integrated with the Ultiboard layout environment. Through extensive resources, templates, and reference design files National Instruments can help you quickly begin creating custom I/O modules, daughter cards, and accessories for platforms that use LabVIEW FPGA - such as CompactRIO and NI Single-Board RIO.
Available resources include:
- Creating a Custom R-Series to M-Series Connector Board with Multisim and Ultiboard
- Using Multisim to Design a Custom CompactRIO Module
- Templates for CompactRIO I/O Module Design
- Customization of a CompactRIO Platform: Breakout Board Design with Multisim and Ultiboard
- Reference Design: Defining a Custom C Series Module to Sense Environmental Stimuli
- Introduction to NI Single-Board RIO Daughter Card Design
Figure 13. NI Multisim and NI Ultiboard offers templates for C Series I/O modules
To learn more about Multisim:
- Multisim Interactive Demo [Learn how to Capture and Simulate Online]
- Multisim 101 Webinar [Introduction to the Multisim Environment]
- What's New in NI Multisim 10.1 [Professional Features]
- Best Practices in Design [Webcast which explores how you can improve design]
11. Learn More
To learn more about FPGA-based control, visit these links:
- CompactRIO success stories, tutorials, and hardware selection guides
- LabVIEW FPGA hardware target information and software demonstrations
- Motion control tutorials and development tools
- Machine vision and image processing technology
- Real-time, processor-based control system technology
- The Many Personalities of NI RIO Technology