1. What Is RIO Technology?
With National Instruments reconfigurable I/O (RIO) technology, you can define your own custom measurement and control hardware circuitry using reconfigurable field-programmable gate array (FPGA) chips and LabVIEW graphical development tools. At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt logic blocks and programmable routing resources, you can configure these chips to implement custom hardware functionality. FPGAs instantly take on a new “personality” when you recompile a different configuration of circuitry. Because FPGA algorithms run with reliability in hardware, they offer benefits such as precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks.
Figure 1. Code compiled for an FPGA runs with determinism in hardware.
In the past, programming an FPGA required expertise in board-level hardware description languages (HDLs) such as VHDL or Verilog. Today, RIO technology has opened the door for anyone to take advantage of FPGAs using higher-level tools such as NI LabVIEW software. With the LabVIEW FPGA Module, you can configure hardware functionality by placing blocks on a LabVIEW block diagram and compile them down to a bit stream containing information on how the FPGA reconfigurable logic blocks should function and be wired together. No other design tool knowledge is required. Using RIO technology, you can rapidly create custom hardware circuitry with high-performance I/O and unprecedented flexibility in system timing control.
2. Introduction to R Series Multifunction RIO
NI R Series multifunction RIO devices offer the best combination of value and performance by integrating FPGA technology with eight analog inputs, eight analog outputs, and 96 digital I/O lines into a single device that is offered on standard PC form factors such as PCI, PCI Express, and PXI/CompactPCI. Using the LabVIEW FPGA Module, you can create your own hardware personalities for intelligent data acquisition, control, digital communications protocols, sensor simulation, and signal processing without in-depth knowledge of hardware description languages.
Figure 2. R Series Multifunction RIO Features
Multifunction R Series devices feature a dedicated 16-bit analog-to-digital converter (ADC) per channel for independent timing and triggering and sampling rates up to 750 kS/s. This provides specialized functionality such as multirate sampling and individual channel triggering, which are outside the capabilities of typical data acquisition hardware. Multifunction R Series devices also include a 16-bit digital-to-analog converter (DAC) for analog output update rates up to 1 MS/s and up to 96 digital I/O lines. Onboard flash memory is used to configure modules and store a startup VI for automatic loading of the FPGA when the system is powered on. Three direct memory access (DMA) channels are also included for high-speed data streaming to a host system.
3. Hardware Reliability
Because LabVIEW FPGA block diagrams execute on the FPGA, you have direct control over the hardware I/O. You can analyze each I/O signal and manipulate it in ways that are not possible with fixed I/O hardware. For example, consider the LabVIEW code in Figure 2, which implements a 16-bit event counter. When executed on a Windows machine, you can count only very low-frequency edges because there is no hardware reliability. However, when implemented with LabVIEW FPGA, the code executes in hardware, and you can achieve performance comparable to a typical data acquisition device that implements counter logic on a fixed ASIC. In addition, with small changes in the code, you can add custom counter functionality, which is not possible with a fixed ASIC device.
Figure 3. Sample LabVIEW FPGA Program – 16-Bit Counter