With the LabVIEW FPGA Module, you use graphical programming to configure the field programmable gate array (FPGA) on a NI RIO device. Together, the LabVIEW FPGA Module and RIO devices provide a flexible platform for creating sophisticated measurement and control systems that were previously possible only with custom-designed hardware.
An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an application-specific integrated circuit (ASIC) chip, you can configure and reconfigure the FPGA for different applications. FPGAs are used in applications where the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. Because FPGAs can be used for implementation of custom algorithms in hardware, they offer benefits such as precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. FPGAs are often used in products for measurement and control, but the end users of these systems generally do not want to develop their own FPGA-based systems.
Historically, programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools, which require overcoming a very steep learning curve. With the LabVIEW FPGA Module, NI has opened FPGA technology to a broader set of engineers who can now define FPGA logic using LabVIEW graphical development. No other design tool knowledge is requires to configure the FPGA logic on RIO devices. Measurement and control engineers can focus primarily on their test and control application, where their expertise lies, rather than the low-level semantics of transferring logic into the cells of the chip.
Additionally, the parallelism of LabVIEW graphical programming is ideally suited for the parallel architecture of FPGAs for implementing synchronous or asynchronous parallel tasks. Finally, because the LabVIEW FPGA Module executes your logic in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically. Figure 1 illustrates many of the NI RIO devices that you can configure using the LabVIEW FPGA Module.
Figure 1. LabVIEW FPGA VI Block Diagram and RIO Hardware Platforms
2. NI RIO Hardware
The LabVIEW FPGA Module provides valuable benefits to measurement and control engineers because of the tight, out-of-the-box integration between LabVIEW software and the commercial off-the-shelf (COTS) hardware architecture of the FPGA and surrounding I/O components. LabVIEW FPGA is continually expanding into many National Instruments platforms.
With the implementation of RIO technology on PCI, PXI, Compact Vision System and CompactRIO, engineers now have the benefits of a COTS platform with the high-performance, flexibility, and customization benefits of FPGAs at their disposal to build measurement and control systems.
National Instruments PCI and PXI R Series plug-in data acquisition devices provide analog and digital data acquisition and control for high-performance, user-configurable timing and synchronization, as well as onboard decision making on a single device. Using these devices, you can extend your NI PXI or PCI system to include high-speed discrete and analog control, custom communication protocols, interfaces to custom sensors, custom data acquisition devices, and precise timing and synchronization.
NI CompactRIO, a platform centered on RIO technology, provides a small, industrially rugged, and modular platform that gives you high-performance I/O and unprecedented flexibility for off-the-shelf embedded systems. You can use NI CompactRIO to build an embedded system for applications such as in-vehicle data acquisition, mobile NVH testing, and embedded machine control systems. Additionally, CompactRIO provides a flexible architecture that leverages off-the-shelf processors such as Freescale PowerPCs, real-time operating systems such as Wind River VxWorks, custom digital logic using Xilinx FPGAs, and I/O from National Instruments and many other vendors. Additionally, using the CompactRIO module development kit, you can leverage this framework to develop your own custom CompactRIO modules. The rugged NI CompactRIO system is industrially rated and certified, and it is designed for greater than 50 g of shock at a temperature range of -40 to 70 °C.
NI Compact Vision System is a rugged machine vision package that withstands the harsh environments common in robotics, automated test, and industrial inspection systems. NI CVS-145x devices offer unprecedented I/O capabilities and network connectivity for distributed machine vision applications. NI CVS-145x systems use IEEE 1394 (FireWire) technology that is compatible with more than 40 cameras with a wide range of functionality, performance, and price. NI CVS-1455 and NI CVS-1456 devices contain reconfigurable FPGAs so you can implement custom counters, timing, or motor control in your machine vision application.
The NI PXI-6653 and NI PXI-6652 timing and synchronization control modules use the trigger bus, star trigger, and system reference clock features of PXI to implement multidevice or multichassis synchronization. The LabVIEW FPGA Module targets the FPGA on the PXI-6653/2 modules to develop custom, user-defined applications that were previously impossible to implement with off-the-shelf hardware. These applications include timing and synchronization techniques, custom triggering, and high-speed analog counters.
3. Creating Custom Performance with LabVIEW FPGA
With the LabVIEW FPGA Module, you configure the operation of the FPGA device by programming in LabVIEW. Because many measurement and control systems are already programmed using LabVIEW, programming FPGAs with LabVIEW is easy since you are using the same LabVIEW graphical development environment. In many instanced programming FPGAs with LabVIEW can be much easier than programming Windows or Real-Time systems with LabVIEW since you do not need to understand LabVIEW scheduling or thread switching.
Once you target the FPGA on an NI RIO device, LabVIEW displays only the functions that can be implemented in the FPGA [Figure 2], further easing the use of LabVIEW to program FPGAs. The LabVIEW FPGA Module Functions palette includes typical LabVIEW structures and functions, such as While Loops, For Loops, Case Structures, and Sequence Structures as well as a dedicated set of LabVIEW FPGA-specific functions for math, signal generation and analysis, linear and nonlinear control, comparison logic, array and cluster manipulation, occurrences, analog and digital I/O, and timing. You can use a combination of these functions to define logic and embed intelligence onto your NI RIO device.
Figure 2. LabVIEW FPGA Functions Palette
Your LabVIEW block diagram is implemented in hardware, which gives you direct control over the RIO hardware I/O. You can analyze and manipulate I/O signals in ways that are not possible with fixed I/O hardware. Figure 3 shows the block diagram for a simple rising-edge counter (one of the many shipping examples for LabVIEW FPGA). Following the data flow makes it very easy to understand the behavior of this counter. We are continuously reading from a digital line and comparing the line status from one iteration to the next. When the digital line state changes the counter increments by one. The counter size is defined by the I32 data type of the counter indicator, making this a 32-bit counter.
Figure 3. Sample LabVIEW FPGA Program – 32-Bit Counter
On a typical data acquisition device, the counter logic is implemented in a fixed ASIC chip such as the DAQ-STC II, and you write your application using the NI-DAQmx VIs. With the LabVIEW FPGA Module, however, you write your own counter implementation in LabVIEW and configure your own counter “chip” on part of the FPGA. Implementing this type of counter in LabVIEW or LabVIEW Real-Time would be difficult since both solutions require software calls and the overhead of an operating system. Because LabVIEW FPGA uses the block diagram to implement your application directly in hardware, this counter has similar performance to the defined counters on a data acquisition device.
This example only details a single simple event counter; however, customizing the counter or creating additional functionality on the NI RIO device, as shown in Figure 4, is merely a matter of changing the LabVIEW code. Unlike traditional PC processors, FPGAs are parallel processors where adding additional loops to your application will not affect the performance of other independent loops.
In Figure 4 the code has been updated to generate a digital pulse every 4 counts and perform an analog control loop. In the top loop, the code is enclosed in a special version of the LabVIEW Timed Loop, the Single Cycle Timed Loop. The Single Cycle Timed Loop executes every clock cycle of the FPGA clock. This means the clock rate of the counter is determined by the FPGA clock rate at compile time; the default is 40 MHz or every 25 nanoseconds. The code generated by the Single-Cycle Timed Loop is also more space efficient, using fewer gates on the FPGA than LabVIEW code defined with a traditional While Loop. Since some structures are not supported in the Single Cycle Timed Loop, such as Analog I/O, we have used a traditional While Loop. In the bottom loop we are reading in an analog input, performing a PID calculation and writing the calculation to an analog output channel. We are timing this loop using the Loop Timing VI that offer resolutions of milliseconds, microseconds, or clock ticks (25ns). This loop will execute at 10 microseconds or 100 kHz.
Figure 4. FPGA and Host Application for Custom Counter and Control Application
While we are using the PID algorithm that ships with LabVIEW FPGA, we can use signal processing IP from a variety of sources. The NI SoftMotion Development Module includes enhanced algorithms for motion control and built-in inputs for a variety of feedback devices including quadrature encoders, and sine cosine encoders. The NI Digital Filter Design toolkit provides functions and interactive tools for design, analysis and implementation of digital filters within LabVIEW FPGA. Additionally, you can link custom VHDL or Verilog IP into a LabVIEW FPGA block diagram using the HDL interface node.
4. FPGA Development Flow
After creating the LabVIEW FPGA VI, you compile the code to run on the NI RIO hardware. Similar to other FPGA development tools, compile time for an FPGA VI can range from minutes to several hours depending on the complexity of your code and the specifications of your development system. To maximize development productivity, with the R Series RIO devices you can use a bit-accurate emulation mode so you can verify the logic of your design before initiating the compile process. When you target the FPGA Device Emulator, LabVIEW accesses I/O from the device and executes the VI logic on the Windows development computer. In this mode, you can use the same debugging tools available in LabVIEW for Windows, such as execution highlighting, probes, and breakpoints.
Once the LabVIEW FPGA code is compiled, you create a LabVIEW host VI to integrate your NI RIO hardware into the rest of your test and control system. Figure 4 illustrates the development process for creating an FPGA application. The host VI uses controls and indicators on the FPGA VI front panel to transfer data between the FPGA on the RIO device and the host processing engine. These front panel objects are represented as data registers within the FPGA. The host computer can be either a PC or PXI controller running Windows or a PC, PXI controller, Compact Vision System, or CompactRIO controller running a real-time operating system (RTOS). In the above example, we exchange the set point, loop rate, analog input, analog output, and count data with the LabVIEW host VI.
Figure 5. Application Development Flow
The NI RIO device driver includes a set of functions shown in Figure 6 to develop a communication interface to the FPGA. The first step in building a host VI is to open a reference to the FPGA VI and RIO device. The Open FPGA VI Reference function, as seen in Figure 4, also downloads and runs the compiled FPGA code during execution. After opening the reference, you read and write to the control and indicator registers on the FPGA using the Read/Write Control function. Once you wire the FPGA reference into this function, you can simply select which controls and indicators you want to read and write to. You can enclose the FPGA Read/Write function within a While Loop to continuously read and write to the FPGA. Finally, the last function within the LabVIEW host VI in Figure 4 is the Close FPGA VI Reference function. The Close FPGA VI Reference function stops the FPGA VI and closes the reference to the device. Now you can download other compiled FPGA VIs to the device to change or modify its functionality.
The LabVIEW host VI can also be used to perform floating-point calculations, data logging, networking, and any calculations that do not fit within the FPGA fabric. For added determinism and reliability, you can run your host application on an RTOS with the LabVIEW Real-Time Module. LabVIEW Real-Time systems provide deterministic processing engines for functions performed synchronously or asynchronously to the FPGA. For example, floating-point arithmetic, including FFTs, PID calculations, and custom control algorithms, are often performed in the LabVIEW Real-Time environment. Relevant data can be stored on a LabVIEW Real-Time system or transferred to a Windows host computer for off-line analysis, data logging, or user interface displays. The architecture for this configuration is shown in Figure 7.
Figure 6. FPGA Interface Palette
There are number of ways to transfer data between the NI RIO device and the LabVIEW Host Application (shown as Time-Critical Interface VI in Figure 7). For single point data transfers, you can synchronously transfer data by generating a physical interrupt from the FPGA to signal data transfer with the host. You can then have the FPGA application wait on interrupt or continue acquiring and processing data. For large data transfers, LabVIEW FPGA includes three Direct Memory Access (DMA) channels. You will use DMA for streaming data from the FPGA device.
5. Performance Benefits of Graphical Programming
Since LabVIEW FPGA implements the graphical block diagrams in the actual hardware, performance for algorithms in LabVIEW FPGA is much better than that of software-based systems. For example, consider an application with eight PID control loops. Using LabVIEW Real-Time to perform eight PID calculations with a PXI-7831R simply for I/O, you can achieve a loop rate around 30 kHz. When you implement an integer-based PID algorithm within the FPGA of an R Series or CompactRIO device, you can achieve loop rates of over 100 kHz for all eight loops. The speed limitation for this control loop is due to the settling time of the A/Ds, as A/D become faster this loop rate will increase. Control loops for digital I/O such as PWM can be performed at over 1 MHz depending on your RIO hardware.
Another benefit of running your LabVIEW code on the FPGA is that you can achieve true simultaneous, parallel processing. There is no operating system on the module that must divide CPU time between several tasks. Consider the application discussed earlier in Figure 4. This application creates two completely independent processors on the FPGA that can operate either synchronously to the FPGA clock or asynchronously. Even within the same While Loop or other structures you can achieve speed improvements by pipelining your code, subsequently performing operations in parallel. You can accomplish this by dividing up your processing, performing the pieces on subsequent iterations of your While Loop. In Figure 8 below, a control algorithm is divided into two pieces.
Figure 8. Pipelining Architecture
In Figure 8, each iteration of the While Loop updates the control output, but the AI and Control 1 operations are performed in parallel with the AO and Control 2 operations. The end result is the algorithm executes faster than an in-line processing architecture would. This simultaneous, parallel processing would not be possible on a platform with a microprocessor and operating system.
Because LabVIEW FPGA can configure low-level hardware design of FPGAs and use them within in a modular system, it is ideal for applications requiring custom hardware. These applications include custom mix of analog, digital, and counter/timer I/O, analog control up to 100 kHz, digital control up to 20 MHz, and interfacing to custom digital protocols.
The LabVIEW FPGA Module brings a new level of timing control and synchronization capability to measurement and control system development. You now have the capability to design your own I/O board, simply by drawing a LabVIEW block diagram. As an example of this, consider a real-time measurement of spark timing of an automotive engine. This is the time delay from the engine’s crankshaft rotating through the zero degree mark, referred to as top dead center (TDC), and the firing of a particular spark plug. To make this measurement, you must measure the crankshaft position and the ignition coil voltage. The typical built-in automotive crank sensor is magnetic and counts the teeth in a gear on the crankshaft, sending out pulses that you can read on a digital input line. There are missing teeth at TDC. Thus to measure spark timing, you must determine, in real-time, when the signal from the crank sensor indicates the missing teeth. Now, also in real-time, you must measure the delay from this event on the digital input, and the analog event of spark firing. By implementing this logic with the LabVIEW FPGA Module, you create a custom I/O device. Whereas most I/O boards return a voltage or a pulse width to the host computer, this device returns spark timing calculated from mixed signal inputs.
There are many types of analog control applications that can benefit from the hardware determinism of RIO hardware and LabVIEW FPGA. With the flexibility of the LabVIEW FPGA Module, you can implement common control algorithms, such as PID, as well as develop customized algorithms for your application. Some examples of analog control include the following:
- Dynamometer control (speed/load)
- Servo-hydraulic or electrodynamic shaker control
- Motor speed or position control
In addition to performing as a complete control system as described previously, you can use RIO hardware in systems for rapid control prototyping (RCP) and hardware-in-the-loop simulation testing of controllers under development. Electronic controllers are common in many products such as vehicles and household appliances. In the early stages of development, before the controller is built, the control algorithms must be tested with the plant—the system to be controlled. To accomplish this, the RCP system behaves as the controller and uses specifically designed algorithms to test the control of the plant. After the preliminary version of the controller is built, it must be validated. For extensive testing, it is often more convenient to simulate the plant and test the controller. This is often referred to as hardware-in-the-loop (HIL) testing.
The LabVIEW FPGA Module extends the LabVIEW platform by building on the capabilities of LabVIEW and the LabVIEW Real-Time Module. Typically, for an HIL or RCP application, you use a LabVIEW Real-Time target as your host processor. Here you will execute the main model and complex processing algorithms. You use the LabVIEW FPGA Module to configure the R Series or CompactRIO chassis to handle the I/O and synchronize with external events. Just as with a fixed-functionality I/O device, the hardware processing happens at a much higher speed than the software processing on the host computer. Within the FPGA, you can customize your own hardware processing, including simulating sensor outputs, generating and decoding PWM signals, and performing onboard decision making based on measured values. With this type of architecture, you can greatly reduce the need for multiprocessor systems that are often used to handle both the simulation and I/O in many systems today.
Manufacturing applications require fast, robust control systems. By using the FPGA on an RIO device to execute the logic of your application, the LabVIEW FPGA Module provides a platform for developing such systems. R Series and CompactRIO devices are able to scan and set multiple digital lines, while making control decisions in a fraction of a microsecond. Because the RIO device running LabVIEW FPGA does not have the overhead of operating system software, such as a real-time operating system or a modification of the Windows kernel there is no possibility of unanticipated latency.
Digital Protocol Emulation
Many applications require that systems interface to devices that speak an uncommon digital protocol. Often, hardware for this is either not available or not affordable. With the LabVIEW FPGA Module, you can take advantage of the high-speed digital processing in hardware to decode and encode messages with a high degree of flexibility. In this way, you configure the FPGA to become an interface module for your communication protocol. Common protocols used include: SPI, I2C, SP/DIFF, RS-232, and more.
Pulse-width modulated (PWM) signals are common in many industries, such as automotive and telecommunications. In a PWM pulse train, the frequency is held constant, and the information is conveyed by the duty cycle—the percentage of time the pulse is high. Many fixed-functionality DAQ devices do not adequately handle rapidly changing duty cycles or allocate a fixed number of channels for static PWM or other operations. With the LabVIEW FPGA Module, you can configure any of the digital lines on RIO hardware to read or write PWM signals as required by your application.
Flexible Encoder Interface
An encoder is a device for measuring speed or position. As a shaft rotates, pulses are generated indicating degrees of rotation. There are many different types of encoders available, and often several types must be used in the same application. With the LabVIEW FPGA Module, you can configure the RIO device to interface to different types of encoders on different digital lines and reconfigure the device for different applications. You can add your own custom functionality, such as reading the counters synchronously with other signals, rather than reading based on input signals to the counters themselves.
By using the LabVIEW FPGA Module, your applications can benefit from the speed and synchronization capability of FPGAs, as well as traditional capabilities such as DAQ, motion control, industrial communication, and others. The dataflow model and inherent parallelism of the LabVIEW graphical programming language provides a highly intuitive environment for developing measurement and control applications for execution in hardware. Using LabVIEW FPGA with LabVIEW and LabVIEW Real-Time, you can address new applications and gain the most performance from your system.
The LabVIEW FPGA Module brings the flexibility, performance, and customization of FPGAs to measurement and control applications. Using NI RIO devices and LabVIEW graphical programming allows you to build flexible and custom devices using COTS platforms where the only previous solution was building custom hardware. The dataflow model and inherent parallelism of the LabVIEW graphical programming language provides a highly intuitive environment for developing measurement and control applications that need execution in hardware. Using LabVIEW FPGA as part of your measurement and control system will add significant flexibility and functionality for applications requiring ultra high-speed control, interfaces to custom digital protocols, or a custom I/O mix of analog, digital, and counters.