Creating a Custom I/O Driver with Simulation Interface Toolkit 3.x

You can use the LabVIEW Simulation Interface Toolkit (SIT) 3.x to run a simulation on a National Instruments real-time controller by mapping model inports and outports to a wide variety of hardware, including National Instruments FPGA, CAN, and DAQ interfaces. You can also map model inports and outports to other hardware, such as an RS-232, GPIB, or 3rd party interface.

The SIT Connection Manager dialog box walks you through configuring a model to run on real-time (RT) hardware. However, you also can construct a custom hardware I/O module by using the Simulation Interface VIs. This document describes how to construct custom hardware I/O.

Note: If you are using third-party or custom hardware, this document assumes you already have a real-time compatible driver (VI- or DLL-based) for that hardware.

1. Using the SIT Connection Manager to Create I/O Mappings and Auto-generate the Driver VIs
2. When You May Need to Create a Custom Hardware I/O Driver Manually
3. The Hardware Driver I/O Architecture
4. Method 1: Adding Capabilities to the Four Custom I/O VIs in Generated Hardware VI
5. Method 2: Adding Four VIs to the IO Base Rate Loop in Template
6. Conclusion

Using the SIT Connection Manager to Create I/O Mappings and Auto-generate the Driver VIs

The driver VI is the VI that communicates between the RT target and the host computer. The driver VI contains mappings from the host VI to the hardware I/O. You can use the the SIT Connection Manager dialog box, available by launching LabVIEW and selecting Tools»SIT Connection Manager from the pull-down menu, to generate a driver VI for the following hardware combinations:

• One or more National Instruments FPGA interfaces (including CompactRIO)
• One or more National instruments CAN interfaces
• A combination of National Instruments FPGA and CAN interfaces
• A single National Instruments DAQ interface

The LabVIEW Help explains how to use the SIT Connection Manager dialog box to create the driver VIs for the above scenarios. In LabVIEW 7.1 you can access the SIT Help by going to Help»Simulation Interface Toolkit Help from the pull-down menu. In LabVIEW 8.0 you can access the help by selecting Help»Search the LabVIEW Help from the pull-down menu and navigating to Toolkits»Simulation Interface Toolkit. The rest of this tutorial assumes a knowledge of how to convert a model into a model DLL, how to create a host VI and driver VIs for one of the scenarios listed above, as well as a knowledge of the basic architecture the Simulation Interface toolkit uses to communicate between the host VI, the model or DLL, and the hardware I/O. Refer to the LabVIEW Help for more information about each of these topics.

When You May Need to Create a Custom Hardware I/O Driver Manually

You need a custom driver VI in the following situations:

• You have multiple National Instruments DAQ interfaces
• You have a combination of one or more National Instruments DAQ interfaces and FPGA or CAN interfaces
• You have one or more serial, GPIB, third-party, or custom I/O interfaces

In any of these situations, you can use the SIT Connection Manager dialog box to create an initial driver VI and then modify this VI to fit your needs.

The examples and screenshots that follow assume a single-rate model, but the concepts also apply for multi-rate models.

The Hardware Driver I/O Architecture

In order to know how to modify the necessary driver VIs it is important to understand the architecture and VIs the SIT Connection Manager uses when it auto-generates the driver VIs. This section describes the VIs that are created by the SIT Connection Manager dialog box and provides information about the VIs you must modify.

Once you create an initial hardware mapping using the SIT Connection Manager dialog box, click the Build Model Files button to build the driver VIs that will be downloaded to your Real-Time target. Figure 1 shows this button.
The hardware I/O driver consists of a top level driver VI, modelname_driver.vi, and a LabVIEW support library modelname_IO.llb. These files exist in the same directory you specified for the model DLL in the SIT Connection Manager dialog box. For example, refer to the Sine Wave example located at labview\examples\Simulation Interface\Sine Wave\sinewave_driver.vi.

The top-level driver VI is created from a template located in the labview\vi.lib\addons\Simulation Interface\_drivertemplates\ directory. Single-rate models use sit driver_single_template_mw_IO.vit as the template. This template creates a top-level driver VI that executes the following steps:

• Initializes the model
• Starts the SIT Server on the target
• Initiates datalogging
• Configures timing parameters
• Starts the hardware loop (the IO Base Rate Loop VI). Figure 2 shows this VI on the block diagram of the driver VI.

For single-rate models, you generally do not need to modify this top-level driver VI. The most important VI is the IO Base Rate Loop VI, which contains the I/O loop that runs for the duration of the simulation and that steps through the simulation, reading and writing data to hardware at each step. This VI is created from a template that is also in the labview\vi.lib\addons\Simulation Interface\_drivertemplates\ directory. The single-rate model template is SIT Base Rate Loop (single rate).vit. The VI created from this template will be located in the support library previously mentioned and will be named modelname_IO IO Base Loop Rate.vi

The IO Base Loop Rate VI performs the following tasks:

1. Initializes the I/O
2. In a loop:
   1. Reads from the hardware inputs.
   2. Runs the SIT Scheduler, which takes the hardware input values just acquired, runs a single step of the simulation, and receives output values from the simulation.
   3. Writes the values returned from the simulation to the hardware outputs.
   4. Probes the values of the simulation and send them to the SIT Server.
   5. Performs any commands the host VI sends.
3. Frees hardware resources after the loop finishes

Looking at the IO Base Loop Rate VI for the Sine Wave example. Notice there are four custom VIs that are correspond to the hardware I/O specified in the SIT Connection Manager dialog box. These VIs are modelname_IO IO Init.vi, modelname_IO IO Read.vi, modelname_IO IO Write.vi, and modelname_IO IO Close.vi. These four VIs are stored in the modelname_IO.llb support library previously mentioned. In this example, modelname is "sinewave". Figure 3 shows the Init, Read, and Write VIs on the block diagram of the base rate loop VI.


The content of these four custom VIs depends on the hardware mappings you defined in the SIT Connection Manager dialog box. As previously mentioned, this dialog box supports only certain types and combinations of hardware mappings. To create a driver for an I/O mappings for hardware combinations not natively supported by the SIT Connection Manager, National Instruments recommends first using the SIT Connection Manager to create the basic driver VI and then adding to this VI to complete the functionality.

You can accomplish this task in two ways:

1. Modify the four custom I/O VIs by adding additional I/O capabilities to these custom VIs. This method is useful in the following situations:
   1. You are not using any National Instruments FPGA, CAN, or DAQ devices for your hardware I/O (These type sof hardware I/O are natively supported by the SIT Connection Manager dialog box).
   2. You are using multiple National Instruments DAQ devices, but no other devices.
   3. You do not plan on modifying the driver VIs much once you initially create them.
      
2. Modify the IO Base Loop Rate template itself by adding VIs that initialize, read from, write to, and close the hardware. This method is useful in the following situations:
   1. You want to use National Instruments DAQ devices and National Instruments CAN or FPGA devices in the same simulation.
   2. You want to use some other combination of National Instruments DAQ devices, National Instruments FPGA or CAN devices, or serial, 3rd party, or custom I/O hardware interfaces.
   3. You plan on modifying the driver VIs after initially created, to use different hardware I/O, or to expand the driver to use additional hardware later.

   Method 1: Adding Capabilities to the Four Custom I/O VIs in Generated Hardware VI
   

An example of using the first method to create a driver that uses two National Instruments DAQ devices and is located in the labview\examples\Simulation Interface\Multiple DAQ Boards\.

The file Multiple DAQ Boards – readme.txt located in the same directory is very useful for understanding how to implement this method. Important highlights from this readme include:

• After you modify the driver VI, do not use the Hardware I/O page of the SIT Connection Manager dialog box. Re-building the driver VI erases any modifications you made to the driver VI. A way to prevent this is described below.
• Open modelname_IO IO Ref.ctl and add additional I/O Task Controls to the cluster. You need one I/O Task Control for each I/O channel you will be configuring.
• Open modelname_IO IO Read.vi and modelname_IO IO Write.vi. You must modify these VIs to read/write the correct inports and outports from the model to the correct I/O channels. For analog input (AI) channels, the data is read and then placed into the presized data array. Similarly, for analog output (AO) channels, the values from the model must be taken out of the presized array in order to be written to the DAQ board outputs. Correct indexing into and out of this array is crucial. Consult the modelname_portsReadme.txt file in the model build directory. This file lists the ordering and widths of all inports and outports in the model.
• When the model contains inports or outports whose width is greater than 1, the index used to place H/W inputs into the model input array might differ from the port number of the inport or outport.
• To determine the index in the model input array of a particular inport, find the set of inports that precede the given inport and add up all of their widths. The sum of the widths is the starting index of the given inport. You can use a similar procedure for outports.

WARNING: If you modify the driver VIs as described above and then use the SIT Connection Manager dialog box to create driver VIs, all the changes you made manually will be overwritten. To reduce the chances of this scenario occurring, rename the top-level driver VI and the support library. If you do rename these files you will need to make a change to the host VI that is created to tell it where to find the driver VIs.

Complete the following steps to rename these files:

1. Rename the driver support library (modelname_IO.llb) so that it will not be overwritten.
2. Rename the top-level driver VI (modelname_driver.vi) so that it will not be overwritten.
3. Open and save and close the top-level driver VI so it relinks the subVIs from the support library to their new paths.
4. Open the host VI created by the SIT Connection Manager dialog box display its block diagram. Right-click the SIT_Meta_Info cluster control, shown in Figure 4, and select Show Control from the shortcut menu.
5. Display the front panel, and scroll to the right until you find the now visible SIT_Meta_Info control. Click the Browse button next to the Model VI Path control, shown in Figure 5, and browse to the top-level driver VI you renamed in step 2.

After you complete these steps, if you do regenerate the driver VIs and host VI using the SIT Connection Manager dialog box, the changes you made to the driver VIs will be preserved. You will need only to repeat steps 4 and 5 to point the host VI to the renamed top-level driver VI.

Method 2: Adding Four VIs to the IO Base Rate Loop in Template

The advantage of the second method is that if you are using National Instruments DAQ, FPGA, or CAN devices for part of the hardware I/O, you can use the SIT Connection Manager dialog box to recreate this part of the driver VI. Because you are modifying only the IO Base Rate template from which the driver VI is created, the additional set of custom hardware VIs will not be affected or overwritten if you rebuild the driver from this dialog box.

For example, you could use the SIT Connection Manager to create the part of the driver that uses National Instruments FPGA devices, then add an additional set of hardware VIs to do I/O with a serial interface. In this scenario you could make changes to the FPGA hardware I/O mappings using the SIT Connection Manager and regenerate the driver without affecting the VIs used to initialize, read from, and write to the serial interface.

Note: As you create these custom hardware VIs, you will need to know what the indexes are into the array of inports and outports. Refer to the previous section of this document, Method 1: Adding Capabilities to the Four Custom I/O VIs, for more information about these concepts.

Complete the following steps to use this method:

1. Make a backup copy of SIT Base Rate Loop (single rate).vit, which is located in the labview\vi.lib\addons\Simulation Interface\_drivertemplates\ directory. The template you modify must retain its original name or the SIT Connection Manager dialog box will not be able to find the template when creating the driver.
2. Create four new custom hardware VIs that mimic the behavior of the four generated Init, Read, Write, and Close VIs. These VIs communicate to any I/O that is not configured by the SIT Connection Manager dialog box. For example, if you configured the driver VI to use a National Instrument DAQ device, the additional VIs you create could be used to communicate with an NI FPGA or third-party serial device.
3. You might want to create a typedef to pass resource names, control parameters needed by the hardware, VISA resource names, or DAQmx Task controls to pass between these four new VIs, similar to the modelname_IO IO Ref.ctl that is used by the hardware VIs it auto-generates.
4. Place the corresponding custom hardware VIs you create on the block diagram directly after their auto-generated counterparts in the SIT Base Rate Loop (single rate).vit template. For example, if you were using a serial interface the VI that initializes the interface would come directly after the sit dum IO Init.vi subVI in the SIT Base Rate Loop (single rate).vit template. Wire the error clusters in such a way to produce correct data flow. Figure 6 shows this template before placing these VIs inside, and Figure 7 shows this template after you place the four custom VIs inside.
5. Save the template. From now on, using the SIT Connection Manager dialog box will generate a driver VI that includes these custom VIs.

Note: If you have multiple SIT applications, you will need to maintain multiple copies of the modified SIT Base Rate Loop (single rate).vit template. Each copy must have a unique name. Rename the appropriate copy to SIT Base Rate Loop (single rate).vit, making sure it is placed in the labview\vi.lib\addons\Simulation Interface\_drivertemplates\ directory, before rebuilding the driver VIs for the model associated with that application.

Below is an example of what the template would look like before and after adding the four additional custom hardware VIs. Using either of the methods mentioned here will allow you to create a driver for your simulation that uses nearly any combination of National Instruments, 3rd party, and custom I/O hardware.

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