PDF1. Configure Counter for Pulse Train Generation
First, you configure a counter for pulse train generation. You can use an external or an internal source (there is a bug with the 20 Mhz internal timebase, to be discussed later). You then configure the pulse specs, which must be 2 or greater. Pulse Spec 1 is the number of active source edges for the delay, and Pulse Spec 2 is the number of active source edges used for the pulse. The delay always comes first. For positive output polarity, the delay is low, or 0 V, and the pulse is high, or 5 V. For negative output polarity, the delay is high, or 5 V, and the pulse is low, or 0 V.In order to use Counter Control with the Wait control code, you must add a timeout. The units for the timeout are in seconds. A timeout is needed in case expected source pulses do not occur.
See Also:
Benefits of Staggering Scan/Update Clock in a Control Loop
2. Put the Counter Control VI in a Loop with the Wait Control Code
Put the Counter Control VI in a loop with the Wait control Code. Wake up edges will be defined in this discussion as source edges that cause Counter Control Wait to wake up. Wake up edges occur every n(PS1+PS2) + PS1-1active source edges, where n=0,1,2,....,and PS1 and PS2 are the pulse specs. When Counter Control Wait is called, it will wait until one active source edge (or wake up edge) just before the active source edge at which the output pulse will occur. For example, if Pulse Spec 1 = Pulse Spec 2 = 5, the Counter Control VI with the Wait control code would wake up at the 4th active source edge, one source edge before the output pulse occurs, see Figure 2. Regardless of the output polarity, the Counter Control VI will wake up one active source edge before the output pulse.
Figure 2. Example Time Sequence
3. Counter Control Wait Sleeps While Waiting
Counter Control Wait causes the thread it is in to sleep while it is waiting. This is useful because if used in a time critical VI, it allows lower priority VIs to run while it is sleeping. No NI-DAQ calls can be made in other VIs while Counter Control Wait is waiting, besides, all NI-DAQ should be done in one time critical thread.
Use flow control to cause your code to execute after Counter Control Wait wakes up.
4. Additional Information
If one or multiple wake up edge occurs before the next time that Counter Control Wait is called, Counter Control Wait will not wait or sleep until the next wake up edge, but will return immediately (it is as if a wake up edge sets a wake up flag, and Counter Control Wait waits for the wake up flag and clears it when it occurs). In this case, if Counter Control Wait is in a time critical VI, all lower priority VIs will not have a chance to run. If you are in the development environment, the user interface will appear unresponsive, since it runs at normal priority. It is as if a wake up edge sets a wake up flag, and Counter Control Wait waits for the wake up flag and clears it when it occurs.
With NI-DAQ 6.9.1, when using the 20 Mhz internal timebase, Counter Control Wait will wake up on every other wake up edge.
