The PXI industry standard has quickly gained adoption and grown in prevalence in automated test systems since its release in 1998. PXI is being selected as the platform of choice for thousands of applications, from areas such as military and aerospace, consumer electronics, and communications, to process control and industrial automation. One of the key elements driving the rapid adoption of PXI is its use of PCI in the communication backplane. Now, as the commercial PC industry drastically improved the available bus bandwidth by evolving PCI to PCI Express, PXI has the ability to meet even more application needs by integrating PCI Express into the PXI standard. Ensuring the successful integration of PCI Express technology into the PXI and CompactPCI backplanes, engineers within the PCI Industrial Manufacturers Group (PICMG), which governs CompactPCI, and the PXI Systems Alliance (PXISA), which governs PXI, have worked to ensure that the PCI Express technology can be integrated into the backplane while still preserving compatibility with the large installed base of existing systems. With PXI Express, users benefit from significantly increased bandwidth, ensured backward compatibility, and additional timing and synchronization features; thus improving upon an already established platform.
2. Enabling New Applications
By taking advantage of PCI Express technology in the backplane, PXI Express increases the available PXI bandwidth from 132 MB/s to 8 GB/s for a more than 60X improvement in bandwidth while still maintaining software and hardware compatibility with PXI modules. With this enhanced performance, PXI can reach into many new application areas, many of which were previously only served by expensive and proprietary hardware. For example, with PCI Express, a digitizer achieves a direct path to the CPU module, through either an embedded controller or a MXI controller to a PC, with a bandwidth of 1 GB/s. This is approximately an 8X improvement over the throughput offered by the 32-bit, 33 MHz PCI bus. Thus, with PCI Express technology, a high-resolution 16-bit IF digitizer or generator can potentially stream continuously to the CPU at bandwidths up to 500 MHz without bus limits or sharing bandwidth with adjacent modules.
Specifically, in automated tests for the military and aerospace industry, the higher bandwidth available in PXI Express provides new solutions for many applications:
• High-bandwidth IF instruments for communications systems test
• Interface to high-speed digital protocols including LVDS-based proprietary protocols, IEEE 1394, fibrechannel, and others
• Large channel count data acquisition systems for structural and acoustic test
• High-speed image acquisition
Figure 1. With the increased data bandwidth and lower latency offered by PCI Express, PXI Express systems can easily address the needs of new application areas such as high-frequency applications, high-speed digital interfaces, and high-speed imaging.
3. Bringing PCI Express Technology to CompactPCI and PXI
PCI Express was introduced to improve upon the PCI bus platform. The most notable PCI Express advancement over PCI is its point-to-point bus topology. The shared bus used for PCI is replaced with a shared switch, which provides each device its own direct access to the bus. Unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline. Data is sent serially in packets through pairs of transmit and receive signals called lanes, which enable 250 MB/s bandwidth per direction, per lane. Multiple lanes can be grouped together into x1 (“by-one”), x2, x4, x8, x12, x16, and x32 lane widths to increase bandwidth to the slot. PCI Express dramatically improves data bandwidth compared to PCI buses, minimizing the need for onboard memory and enabling faster data streaming. For instance, with a x16 slot, users can achieve up to 4 GB/s of dedicated bandwidth as opposed to the 132 MB/s shared across all devices of the 32 bit, 33 MHz PCI.
To successfully integrate PCI Express into CompactPCI and PXI and still maintain backward compatibility, the PICMG (www.picmg.org) and the PXISA (www.pxisa.org) executed coordinated plans to ensure a smooth transition. Since PXI is based on the CompactPCI specification, these efforts to integrate PCI Express first began with CompactPCI Express in early 2004. Defining the fundamental mechanical and electrical features of CompactPCI Express systems, the CompactPCI Express specification in turn defines the mechanical and electrical features of PXI Express systems. Released June 27, 2005, the CompactPCI Express specification includes the selection of connectors to support PCI Express, definitions of slots and board mechanicals, definitions of slots and board electrical signals, and compliance-testing requirements. In May 2005, work on the PXI Express specification began, and in September 2005 the PXI Express specification passed. The PXI Express specification takes the CompactPCI Express technology and adds specifications for PXI compatibility, timing and synchronization, and system software frameworks.
Because the CompactPCI/PXI Express backplane, shown in Figure 2 below, integrates PCI Express while still preserving compatibility with current PXI modules, users benefit from increasing bandwidth while maintaining backward compatibility with existing systems. PXI Express specifies PXI Express hybrid slots to deliver signals for both PCI and PCI Express. With PCI Express electrical lines connecting the system slot controller to the hybrid slots of the backplane, PXI Express provides a high-bandwidth path from the controller to backplane slots. Using an inexpensive PCI Express-to-PCI bridge, PXI Express provides PCI signaling to all PXI and PXI Express slots to ensure compatibility with PXI modules on the backplane. With the ability to support up to a x16 PCI Express link in addition to a x8 link, the system controller slot provides a total of 8 GB/s bandwidth to the PXI backplane, representing more than a 60X improvement in PXI backplane throughput.
Figure 2. While preserving compatibility with existing PXI modules throughout all slots, this eight-slot backplane adds three new high-performance slots at 1 GB/s dedicated bandwidth each.
By taking advantage of the available pins on the high-density PXI backplane, the PXI Express hybrid slots are capable of delivering signals for both PCI and PCI Express. In doing so, these PXI Express hybrid slots provide backward compatibility that is not available with desktop PC card-edge connectors, where a single slot cannot support both PCI and PCI Express signaling. Thus, the hybrid slot allows you to install a PXI module that uses PCI signaling or a future high-performance PXI Express module that uses PCI Express signaling.
In Figure 3, the diagram of the PXI Express hybrid slot demonstrates how it provides compatibility to both PXI and PXI Express. The P1 and XP4 connectors retain the PCI signaling and PXI timing and synchronization signals of PXI today. Using the new XP3 connector, the hybrid slot provides connectivity for x8 PCI Express as well as pins for additional timing and synchronization.
Figure 3. Unlike slots in desktop PCs, the new PXI Express hybrid peripheral slot provides hardware compatibility by using the extra area for pins on the backplane to install modules with either PCI or PCI Express signaling in a single slot.
4. Maintaining Software Compatibility
In addition to providing hardware compatibility through hybrid slots, PXI Express systems also provide software compatibility so that engineers can preserve their investment in existing software. PCI Express software compatibility is guaranteed through the PCI Special Interest Group (PCI-SIG), which includes companies like Intel and Dell. Because PCI Express uses the same driver and OS model as PCI, the specification guarantees that engineers have complete software compatibility among PCI-based systems, for example PXI, and PCI Express-based systems, such as PXI Express. As a result, vendors and customers do not need to change driver or application software for PCI Express-based systems.
By maintaining software compatibility between PCI and PCI Express technology, the specification drastically reduces cost for vendors and integrators to insert new PCI Express technology into existing test systems. With hardware compatibility provided by the hybrid slot and software compatibility, the cost of adding PXI Express technology is minimal.
5. Providing Additional Timing and Synchronization Features
PXI Express not only retains the timing and synchronization features of PXI, but it also adds several new synchronization features by taking advantage of the existing differential connectors required in PXI and technological advances that provide higher performance, low-cost differential signaling. Building on these existing capabilities in PXI, PXI Express provides the additional timing and synchronization features of a differential system clock, differential signaling, and differential star triggers, as shown in Figure 4. By using differential clocking and synchronization, PXI Express systems benefit from increased noise immunity for instrumentation clocks and the ability to transmit at higher frequency clocks. In addition to allowing engineers to improve the performance of the system, high-frequency clocks also match well with modern processes and allow lower cost products to remove clock multiplication circuits. With the industry’s best synchronization and latency, PXI Express improves the measurement accuracy and test time of high bandwidth applications.
Figure 4. By building upon the existing capabilities of the PXI platform, PXI Express provides additional timing and synchronization features to achieve better measurement accuracy.
6. The Future of PXI
While the integration of PCI Express technology into PXI will allow PXI Express to reach new applications, many existing PXI applications will not benefit from the enhanced performance of PXI Express. For example, hardware such as digital multimeters (DMMs), switches, industrial I/O, bus interfaces, and many mainstream generators and analyzers will not benefit from the additional backplane bandwidth. Thus, one of the most valuable aspects of the PXI Express specification is its ability to route both PCI and PCI Express signaling to new slots. As a result, engineers should not expect instrument manufacturers to redesign all current boards for PXI Express; rather, many instrument manufacturers will continue to base PXI products on PCI signaling because the current PCI architecture serves the need and PCI signaling is provided to all slots.
In January 2007, the PCI-SIG, the organization chartered with the development of the PCI bus specification, announced the availability of the PCI Express 2.0 specification (also known as PCI Express Gen2). The PCI Express Gen2 specification doubles the data transfer rate from Gen1 by doubling the bus bit rate from 2.5 GT/s to 5.0 GT/s while keeping full backward hardware and software compatibility to PCI Express Gen1. Engineers and scientists can expect PXI Express products to incorporate this development to further enhance the capabilities of the PXI platform.
 CompactPCI Express PICMG EXP.0 R1.0 Specification, PCI Industrial Manufacturers Group, July 27 2005
 PXI-5 PXI Express Hardware Specification Revision 0.5, PXI Systems Alliance, July 15 2005
 G. Caesar, PXI Embraces New Commercial Standards, Instrumentation Newsletter, Q2 2005.
 J Titus, PXI gets the Express Treatment, ECN, July 1 2005. http://www.ecnmag.com/article/CA623714.html
 L Gutterman, PXI Express?, PXI Technology Review, Spring 2005.
 Introduction to PCI Express, National Instruments