Under the Hood of the NI PXIe-1491

Learn about the technologies and architectures behind the NI PXIe-1491 HDMI and mobile HD analyzer.

1. Interfaces
2. Architecture and Key Components
3. Data Bandwidth
4. Audio Return Channel
5. Conclusion

Interfaces

The NI PXIe-1491 HDMI and mobile HD analyzer features two independent inputs: 

• One high-definition multimedia interface (HDMI) input called HDMI IN
• One input for mobile devices, such as smartphones, called MOBILE IN 

By separating HDMI and mobile inputs, the NI PXIe-1491 helps the user connect both HDMI and mobile devices at the same time. Separate mobile and HDMI inputs also ensure full HDMI Ethernet and Audio Return Channel (HEAC) functionality on the HDMI input. 

HDMI Input

The HDMI input includes support for the following features:

• Bidirectional HDMI Ethernet Channel (HEC) and the Audio Return Channel (ARC), jointly known as HEAC
• Consumer Electronics Control (CEC)
• Display Data Channel (DDC)
• Hot Plug Detect (HPD)
• High-bandwidth Digital Content Protection (HDCP)

Figure 1. Front Panel of the NI PXIe-1491 HDMI and Mobile HD Analyzer Showing Mobile In, HDMI In, Monitor Out, and an Ethernet Port for HDMI Ethernet Channel (HEC) Access

Monitor Output

The HDMI monitor output (called MONITOR OUT) provides a re-encrypted copy of the content from the selected input. The monitor output is an HDMI signal, no matter if you have selected the HDMI input or mobile input. The SYNC LED is lit if the NI PXIe-1491 recognizes an HDMI signal while the HDMI IN is selected or a mobile signal while the MOBILE IN is selected. 

RJ-45 Connector

The RJ-45 connector gives you transparent access to the bidirectional HDMI Ethernet Channel (HEC) for the HDMI input. If the NI PXIe-1491 is connected to an HDMI source that supports HEC, you may transfer 100 BASE-T data between these two HDMI devices for various purposes. Seen from the user's perspective, the NI PXIe-1491 is an Ethernet switch, but one of the ports of this switch has the unusual connection in the form of an HDMI cable. The necessary signaling and current switching circuitry to transmit and receive the Ethernet data over the HDMI cable is defined by the HDMI specification. The HDMI source includes circuitry similar to the NI PXIe-1491 to provide Ethernet access.

Cabling

All three connectors—HDMI IN, MOBILE IN, and MONITOR OUT—are HDMI Type A receptacles and therefore require a cable with an HDMI Type A plug. For example, one appropriate cable to use for attaching a mobile device's micro-USB connector to the NI PXIe-1491 module's MOBILE IN connector would be a Micro-USB to HDMI Type A adapter cable, which is available from different vendors.

Note: Never try to connect a monitor to anything but the monitor output of the NI PXIe-1491. In other words, avoid connecting two HDMI sinks together. You might make this mistake because the HDMI Type A plug is used for both HDMI sources and sinks, and the HDMI cable has the same HDMI Type A plug in both ends. If you do so, the termination rail of one sink may try to power the other, especially if one of the two sinks is not powered up.

Pin Assignments

Though the inputs on the NI PXIe-1491 require the same cable types, the behind-the-scenes pin mapping of the HDMI and mobile interfaces is different. Table 1 summarizes the pin mapping for the three HDMI Type A receptacles used in the NI PXIe-1491:

Figure 2. HDMI Type A Pinout

Table 1. Pin Assignments for Each of the Three Interfaces on the NI PXIe-1491

Mobile Pin Assignment

The mobile input of the NI PXIe-1491 detects the presence of a non-HDMI source by monitoring the level on pin 2. The NI PXIe-1491 expects that pin 2 of the mobile input is pulled high. With no plug inserted, or with an HDMI cable inserted, pin 2 remains low, and the NI PXIe-1491 interprets this as if no proper plug has been inserted. With the right HDMI Type A plug for mobile applications, pin 2 is pulled high by having a resistor inside the shell between pins 2 and 15, which the NI PXIe-1491 conveniently pulls to 5 V through a 47 kΩ resistor.

The NI PXIe-1491 includes an upstream 5 V power to the mobile source from the mobile input connector. This power connection, typically referred to as “Voltage bus” or “VBUS,” is normally used for charging mobile devices. Note that pin 18, which is used for VBUS upstream power, is also used for downstream power in HDMI. For that reason, the internal circuitry of the NI PXIe-1491 ensures that the VBUS upstream power is left disabled unless both of the following two conditions are met: (1) a logic high voltage is detected on pin 2, thereby indicating that a non-HDMI cable has been plugged in and (2) the user has enabled VBUS power.

Architecture and Key Components

The block diagram in Figure 3 shows the main signals and the key components of the NI PXIe-1491. The left side shows the user-accessible interfaces—the MOBILE IN, HDMI IN, MONITOR OUT, and RJ-45 connector for the LAN/HEC LINK. The signal flow is basically from left to right, ending at the PXI Express backplane.

Figure 3. The Architecture and Components of the NI PXIe-1491

The port processor is the termination point for the incoming HDMI and mobile data. The device is the SiI9489 from Silicon Image, a leading provider of HDMI devices and one of the HDMI founders. The processor handles all HPCP decryption and forwards the data to the HDMI receiver. The Transition Minimized Differential Signaling (TMDS) cores of the port processor and the HDMI receiver run up to 225 MHz, thus supporting resolutions up to 1920x1080p @ 60 Hz in 12-bit deep color on the HDMI input. The mobile input supports up to 1080p @ 30 Hz, or 1080i/720p @ 60 Hz. The port processor also includes an HDMI transmitter with HDCP re-encryption for the monitor output.

The EDID resides inside the port processor in nonvolatile memory, and can be read by the HDMI source even when the NI PXIe-1491 is powered off. The contents of the EDID can be changed by software interaction through the programming interface of the FPGA.

The port processor also includes the processing block for the communication bus, normally known as CBUS, for the mobile input. This processing block, together with the software used with the NI PXIe-1491, takes care of the protocol between the mobile device and the mobile input. The pull-up and pull-down circuitry that needs to be exercised as a part of the CBUS protocol is located inside the port processor.

Finally, the port processor includes vital parts of the CEC handling thanks to its built-in CEC controller. The NI PXIe-1491 uses the controller and its high-level register interface for selected parts of the CEC signaling. Additional CEC circuitry in the NI PXIe-1491 complements the CEC controller in the port processor to enhance the CEC functionality. The software used with the NI PXIe-1491 determines how the CEC controller and the external CEC circuitry operate.

The HDMI receiver, the SiI9135 from Silicon Image, receives the TMDS data from the port processor, demultiplexes the video and audio data, and outputs this in parallel on a number of LVCMOS signals to the FPGA via the CPLD, which serves as a level translator. The HDMI receiver can handle up to eight channels of uncompressed digital audio and may pass through different formats of encoded (in other words, compressed) audio. The software used with the NI PXIe-1491 determines which audio format to support. The HDMI receiver recovers the audio clock from the incoming video clock in accordance with the HDMI specification. The video data and the audio data are treated independently, as belonging to two independent clock domains, going from the HDMI receiver into the FPGA. Inside the FPGA, the video and audio data are formatted transparently for time-accurate transfer over the PXI Express backplane to preserve lip sync.

The FPGA is at the heart of the NI PXIe-1491 design. The tasks of this powerful FPGA, the LX130T from the Xilinx Virtex-6 family, span over I²C communication, data formatting, DDC and CEC handling, ARC generation, region of interest (ROI) segmenting, conversion features, and eventually real-time analysis, all of which are determined by the actual software being used with the NI PXIe-1491. The FPGA includes a first-in-first-out (FIFO) memory buffer for the signal formatting. The FPGA design reflects NI’s vast experience with VHDL programming and offers the flexibility and power needed for HDMI and mobile analysis. Due to the elaborate design, and to prevent unauthorized access to the audiovisual content, the FPGA is protected by encryption.

The interface to the PXI Express backplane is handled by NI-STC3, the technology that fuels the timing, triggering, synchronization, and bus-interfacing features of a number of products from National Instruments, including the NI PXIe-1491. Using NI-STC3 technology combined with the FPGA, you can accomplish different trigger operations with the NI PXIe-1491, depending on the actual software.

The last key component to pay attention to is the LAN9303, a managed Ethernet switch with three ports. This is the device that provides the physical access to the Ethernet data to and from the port processor and thereby to the HEC in the HDMI cable. Like other features of the NI PXIe-1491, HEC/Ethernet support depends on the software used with the NI PXIe-1491.

Data Bandwidth

The NI PXIe-1491 handles incredible amounts of data. At the highest resolution, 1920x1080p @ 60 Hz with 12-bit deep color components, the raw TMDS data rate is 6.68 Gbit/s (835 MB/s), and the active video area alone represents 4.48 Gbit/s (600 MB/s) of payload into the FPGA. On the PXI Express backplane, the aggregate data rate is the sum of audio and video payload, plus auxiliary data and formatting overhead. If you acquire sequences, the PXI Express chassis and host has to cope with a very high sustained data rate.

The actual PXI Express backplane bandwidth capability needed to sustain the streaming of the active image and the audio data depends on several parameters. It depends on not only the image size, frame, and sample rates but also the size of the on-FPGA FIFO and the ratio between the active image and the blanking interval.

Table 2 presents the theoretical amount of data streamed depending on the selected image format and audio settings. The two columns on the right are defined as follows:

Average PXI Express bandwidth: This represents the streaming requirements averaged over an entire frame, including vertical and horizontal blanking intervals. These values are relevant to calculate the requirements at the host side (mainly the CPU).

Peak PXI Express bandwidth: This represents the actual worst case streaming rate averaged over at least one entire line, including the horizontal blanking interval. The FIFO inside the FPGA can buffer a number of lines but cannot store an entire frame. Use the values in this column to estimate the true PXI Express backplane requirements.

Table 2. Resolutions With Frame Rates and Their Corresponding Data Bandwidth

The Table 2 calculations are presented with the assumption that you need to acquire the entire active image. However, if you acquire only a portion of the image (an ROI), the PXI Express bandwidth may drop, depending on the chosen picture width and number of lines. The resulting PXI Express bandwidth is close to proportional with the chosen picture width, which makes it easy to fit the NI PXIe-1491 into a system with insufficient PXI Express bandwidth merely by setting up the ROI width. On the other hand, you are required to reduce the ROI picture height substantially to get a similar bandwidth reduction because the backplane has to handle the data bandwidth averaged over the number of lines stored in the FIFO in the FPGA.

For more information on bandwidth issues and which PXI Express chassis and controller to use, contact your nearest NI representative.

Audio Return Channel

HEAC Technology

Thanks to ARC technology, a TV viewer can enjoy the sound from the speaker system connected to a media receiver, for instance, rather than from the small speakers in the TV set, without additional cables. The ARC and the HEC features cleverly use the existing wires in the HDMI connection: The Utility/HEAC+ is on pin 14, and HPD/HEAC- is on pin 19. The HEC signal is applied as a balanced signal on the HEAC pair, while ARC is applied as a common-mode signal on the HEAC pair.

The port processor of the NI PXIe-1491 includes all the necessary circuitry to provide upstream (ARC) technology in addition to the HEC. All it requires is that the HDMI source supports ARC. The design of the NI PXIe-1491 also allows HPD and HEAC to coexist.[FE1]  

Software-Programmable Audio

In the NI PXIe-1491, the audio data for the ARC comes from the FPGA, so you can use software to configure audio testing of the HDMI source. For example, you can use software to select different sample rates. The FPGA provides audio data formatted as S/PDIF, which is processed transparently by the circuitry in the port processor. The clock for the S/PDIF generator inside the FPGA comes from the programmable clock generator, which gets its clock from a 27 MHz temperature-compensated crystal oscillator (TCXO). This oscillator determines the frequency accuracy of the S/PDIF signal and eventually of the recovered upstream audio signal from the HDMI receiver.

 Single-Mode Versus Common-Mode ARC 

According to the HDMI specification, an HDMI sink may optionally apply ARC on a single wire only, the Utility/HEAC+ connection. This is known as single-mode ARC. Single-mode ARC does not allow for HEC support, however, so to provide HEC and ARC on the same connector, the NI PXIe-1491 supports common-mode ARC only.

 Cabling for HEAC Support

To maintain the ARC and HEC signal integrity and to ensure error-free TMDS data transfer at the highest resolutions, you need to use an HDMI cable labeled “High Speed with Ethernet” between the HDMI source and the HDMI input of the NI PXIe-1491. For the monitor output, you need a “High Speed” HDMI cable to cope with the high resolutions; you do not need a “High Speed with Ethernet” cable for the monitor output because there’s no ARC or HEC support.

Conclusion

The technologies and advanced architecture of the NI PXIe-1491 reflect that of the interfaces in which this analyzer is designed to test. 

The terms HDMI and HDMI High-Definition Multimedia Interface and the HDMI Logo are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. All other trademarks and registered trademarks are the property of their respective owners in the United States and other countries.

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