NI Single-Board RIO General-Purpose Inverter Controller Features

Publish Date: Dec 05, 2012 | 5 Ratings | 4.20 out of 5 | Print

Table of Contents

  1. Overview
  2. Software Features
  3. Hardware Features
  4. Next Steps

1. Overview

Move your grid-tied power converter product from design to high-volume commercial deployment faster with the NI Single-Board RIO general-purpose inverter controller (GPIC). The NI Single-Board RIO GPIC takes advantage of the industry-proven LabVIEW graphical system design environment for the design, development, and deployment of inverter control applications. LabVIEW is an intuitive graphical programming environment that helps you quickly develop powerful applications with professional UIs using drag-and-drop graphical components and flexible, high-level APIs.

LabVIEW and the NI Single-Board RIO GPIC make field-programmable gate array (FPGA) technology easily accessible, so you can define your own control circuitry while reducing the complexity and costs associated with traditional custom hardware.

Summary of Key Features

• Enables a revolutionary new embedded system design approach for rapid commercialization of advanced, field-reconfigurable digital energy conversion systems.
• Save an average of 114 person-months and $950,000 USD in development cost by completing your project in 6.2 months rather than 12.5 months with a team size of 4.8 rather than 11.5 for the conventional embedded systems design.
• Rather than spending 70 percent of your FPGA development cost on I/O interfaces using register level Verilog/VHDL programming, high level graphical system design tools enable your development team to focus 90 percent of software engineering development costs on control algorithm development and verification testing.
• Pre-validated, deployment-ready embedded with comprehensive graphical system design toolchain for rapid commercial deployment of advanced FPGA-based power electronics control systems without requiring any knowledge of register level languages such as Verilog and VHDL.
• Standard set of I/O and reconfigurable FPGA carefully chosen to meet the specific control, I/O, performance and cost needs of most smart grid power electronics applications, including DC-to-AC, AC-to-DC, DC-to-DC and AC-to-AC converters for flexible AC transmission systems, renewable energy generation, energy storage and variable speed drive applications.
• Hardware parallel Xilinx Spartan-6™ FPGA with 58 DSP cores outperforms typical dual-core DSPs by a factor of 40x, 24x and 10x, with regards to performance per dollar, per chip and per watt respectively.
• Embedded 400 MHz PowerPC processor with VxWorks RTOS supports smart grid networking protocols DNP3, IEC 60870-5 and IEC 61850, onboard COMTRADE (IEEE 37.111) data logging and standard three-phase IEC, EN, and IEEE power quality analysis

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2. Software Features

Graphical Co-Simulation (Multisim, LabVIEW FPGA Module)

You now can design LabVIEW FPGA control code in a full-featured power electronics co-simulation environment. This means you can rapidly develop and validate advanced high-performance power electronics, and control IP and deploy it, on the NI Single-Board RIO GPIC—without knowledge of the VHSIC hardware description language (VHDL) or Verilog.

Multisim is a simulation program with the integrated circuit emphasis (SPICE) simulation environment for designing, prototyping, and testing electrical circuits. You can quickly and intuitively create power electronic circuits by selecting various power electronic components (motors, buck-boost converters, electromagnetic interference filters, PWM controllers, and many more) from a large set of predefined SPICE models from leading semiconductor manufacturers such as Analog Devices, NXP, ON Semiconductor, and Texas Instruments; placing them on the workspace; and wiring them together.

Figure 1. Multisim Environment

Multisim is fully integrated with LabVIEW so you can simultaneously test your control algorithm through point-by-point simulation between Multisim and LabVIEW and compare the results to real-time data from the actual hardware connected to the FPGA board.

Figure 2. LabVIEW Multisim Co-Simulation

With LabVIEW and Multisim co-simulation, you can develop LabVIEW FPGA code within a high-fidelity simulation environment that captures the interaction between the digital control system and analog power electronics. During LabVIEW FPGA and Multisim co-simulation, the two respective simulators perform nonlinear time-domain analysis concurrently, exchange data at the end of each time step, and negotiate future time steps. This results in tightly integrated, accurate simulation. You can capture the fast transient behavior of the analog circuitry and its interaction with the FPGA-based control system. For example, if the current in an inductor is ringing, the simulation automatically slows down to capture the effect on the digital control system.

Thus, you can develop actual LabVIEW FPGA code within the simulation environment and move it to a physical FPGA target with little effort. The LabVIEW environment supports a completely bidirectional development path. Changes made to the graphical code at any stage—from prototype to postproduction—automatically update anywhere that code is referenced in your application.

Related Links:
Design Guide to Power Electronics Co-Simulation With Multisim and LabVIEW
How to Design and Simulate a Brushed DC Motor H-Bridge Circuit Using NI Multisim and LabVIEW
Complete System Simulation of a Three-Phase Inverter Using NI Multisim and LabVIEW

Algorithm Development Tools

Accelerate the development and testing of your control algorithms with the LabVIEW Control Design and Simulation Module. This module features tools to construct plant and control models using transfer-function, state-space, or zero-pole-gain representation; analyze system performance with tools such as step response, pole-zero maps, and Bode plots; and simulate system behavior.

Figure 3. The LabVIEW Control Design and Simulation Module

Using the LabVIEW toolchain, you can develop a variety of control algorithms—from simple proportional integral derivative (PID) control to advanced dynamic control such as a model-predictive control. You can build your plant model from first principles using the Control Design and Simulation Palette, or import it from Multisim. To accelerate prototype development, you can import FPGA nodes into your model for accurate hardware I/O representation.

The example below illustrates a DC brushed motor drive controller that was designed using the LabVIEW Control Design and Simulation Module and simulated using LabVIEW and Multisim co-simulation.

Figure 4. Closed-Loop System Simulation of a Brushed DC Motor Controller

  1. Speed quadrature decoder
  2. Continuous-time programmable interrupter (PI) controller
  3. PWM generator
  4. H-bridge driver
  5. Multisim brushed DC motor plant

The controller consists of a quadrature decoder, a PI controller, a PWM generator, and an H-bridge driver (items 1 through 4 in Figure 4). For this design, the default onboard 40 MHz FPGA clock permits the generation of a high-resolution, 20 kHz PWM digital pulse with small duty cycles and dead times. The FPGA nodes in the simulation diagram are configured for discrete time execution to simulate the precise timing behavior of the code as it executes on the FPGA. LabVIEW FPGA is extremely well-suited for inverter-control algorithm development, taking advantage of parallel code execution and low latency. Being able to simulate the FPGA behavior during the controller design stage ensures accurate system performance during the deployment stage.

Once the algorithm is designed, you can easily deploy dynamic systems to real-time hardware targets without generating code by using the LabVIEW Real-Time Module for rapid control prototyping and hardware-in-the-loop (HIL) applications.

Related Links:
LabVIEW Control Design User Manual

Development Libraries and IP Cores

With the LabVIEW Electrical Power Suite and Power Electronics IP Core Library, you can reduce your development time and engineering cost by taking advantage of the built-in VIs (LabVIEW code) for a variety of applications. Using the suite, you can create applications that measure, analyze, monitor, and record electrical power parameters. You can use the Electrical Power VIs to measure voltage, current, and frequency; measure power and energy values; analyze voltage and current events; and aggregate and log data.

Figure 5. LabVIEW Electrical Power Suite Functions Palette

The LabVIEW Electrical Power Suite complies with the following standards:

  • EN 50160: 2007, Voltage Characteristics of Electricity Supplied by Public Distribution Networks
  • IEC 61000-4-7: 2002, Electromagnetic Compatibility (EMC), Parts 4-7: Testing and Measurement Techniques—General Guide on Harmonics and Interharmonics Measurements and Instrumentation, for Power Supply Systems and Equipment Connected Thereto
  • IEC 61000-4-15: 2010, Electromagnetic Compatibility (EMC), Parts 4-15: Testing and Measurement Techniques—Flickermeter—Functional and Design Specifications
  • IEC 61000-4-30: 2008, Electromagnetic Compatibility (EMC), Parts 4-30: Testing and Measurement Techniques—Power Quality Measurement Methods
  • IEEE Std C37.111: 1999, IEEE Standard Common Format for Transient Data Exchange (COMTRADE) for Power Systems

IP cores for power electronics and motion control (part of the LabVIEW NI SoftMotion Module) help you implement ready-to-use IP cores for a variety of functions, including trapezoidal and space-vector commutation for three-phase permanent magnet synchronous and brushless DC motor/generators and inverters; Clarke and Park transforms; three-phase phase-locked loop; matrix-vector multiply; and multichannel PID algorithms.

Figure 6. IP Core Library

Related Links:
New Power Electronics IP Library for LabVIEW FPGA (included with LabVIEW NI SoftMotion 2011 f1)

Smart-Grid Ready

Make your power converter application smart-grid-ready by taking advantage of LabVIEW compatibility with the Distributed Network Protocol (DNP3) and IEC 60870-5 open-communication protocols. The NI-IndCom software driver for DNP3 and IEC 60870-5 gives you access to LabVIEW functions used to create DNP3 and IEC 60870-5 outstation applications. You can program these functions on Windows computers for development and deploy them on the NI Single-Board RIO GPIC for field applications.

Figure 7. DNP3 and IEC 60870-5 LabVIEW VIs

The software driver supports Ethernet and serial communication, file transfer, and time synchronization between master and outstation. You also can use multiple communication channels per outstation and multiple sessions (logical devices) per channel.

Below is the analog input example program included in the driver software. This section steps through the basic functions and properties used for programming a DNP3 outstation in LabVIEW.

Figure 8. DNP3 Analog Input Example Program

  1. The Create Outstation function turns the LabVIEW target into a DNP3 outstation and sets the scan rate for checking inputs and sending responses.
  2. The Create Channel function creates a communication channel that encapsulates the physical layer, link layer, and transport function of the DNP3. It also sets the ports or IP addresses for masters that are allowed to connect to the outstation. Multiple channels may be created per outstation. 
  3. The Create Session function creates a connection between a local device (server) and a remote device (client) within a communication channel. Multiple sessions may be created per communication channel. 
  4. The Write function writes to a certain data point index using one of eight data types, including analog input. It can also generate an associated event or object flag. 
  5. The Destroy Session function destroys the session created by the Create Session function. 
  6. The Destroy Channel function destroys the channel created by the Create Channel function. 
  7. The Destroy Outstation function destroys the outstation reference created by the Create Outstation function.

NI-IndCom for DNP3 contains the capability for a master station to upload and download files from the outstation programmed with LabVIEW. For outstation time synchronization, use the clock time properties to set the frequency of clock synchronization or manually request a resynchronization.

Related Links:
NI Industrial Communications for DNP3

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3. Hardware Features

NI Single-Board RIO GPIC I/O

By using an NI 9683 off-the-shelf, prevalidated GPIC board, you accelerate the time to market of your power electronics control application. The NI Single-Board RIO GPIC provides a complete set of hardware I/O for a variety of applications, ranging from inverter control and interface with intelligent power modules to smart-grid monitoring. NI 9683 hardware I/O includes the following:

  • High-speed simultaneous analog input for primary- and secondary-side voltage/current measurement
  • Low-speed analog input and output for system-level control and monitoring
  • High-speed digital output for insulated-gate bipolar transistor and metal-oxide-semiconductor field-effect transistor switching
  • General-purpose digital input and output for system-level control and monitoring
  • Contactor digital output for direct connection to 24 VDC contactors

Figure 9. NI Single-Board RIO GPIC I/O

All inputs and outputs are connected through the RIO Mezzanine Card (RMC) connector to the NI sbRIO-9606 controller board. The high-speed, high-bandwidth RMC connector provides direct access to FPGA digital I/O lines as well as certain processor-specific functions. The FPGA I/O is connected to the RMC connector through a series of termination resistors, and the FPGA drive strengths and onboard signal termination have been tuned to support a wide range of applications.

Figure 10. Connection Between NI Single-Board RIO GPIC I/O and FPGA

You can directly access the I/O nodes in the NI LabVIEW FPGA graphical system design environment, which does not require any knowledge of register-level programming languages such as Verilog or VHDL, for rapid development of digital logic and control algorithms.

Figure 11. Example Counter

Figure 11 shows a simple VI that counts the number of loop iterations between rising edges on DIO0. Notice that the single-cycle Timed Loop is timed using an 80 MHz derived clock and is registering DIO0 at this rate. The single-cycle Timed Loop is one of the many graphical components in the LabVIEW FPGA environment that simplifies the implementation of complex digital logic on the FPGA.

Related Links:
NI RMC Digital I/O Capabilities

RMC Connector

NI Single-Board RIO Features

The NI sbRIO-9606 embedded control and acquisition device integrates a real-time processor, a user-reconfigurable FPGA, and I/O on a single printed circuit board (PCB). It features a 400 MHz PowerPC processor with a VxWorks real-time OS, a Xilinx Spartan-6 LX45 FPGA, and an RMC connector. The high-speed, high-bandwidth RMC connector provides direct access to 96 3.3 V digital I/O FPGA lines as well as certain processor-specific functions. Having direct access to the FPGA I/O and processor functions means you can achieve low-level timing customization and I/O signal processing for your power electronics control applications.

Figure 12. NI sbRIO-9606 Device

You can directly access all FPGA I/O in the LabVIEW FPGA environment. LabVIEW contains built-in data transfer mechanisms to pass data from the I/O to the FPGA, and from the FPGA to the embedded processor, via a high-speed PCI bus for real-time analysis, postprocessing, data logging, and communication to a networked host computer.


You can use the built-in 10/100 Mbit/s Ethernet port to conduct programmatic communication over the network and host built-in Web (HTTP) and file (FTP) servers. The sbRIO-9606 also features integrated controller area network, RS232 serial, and USB ports for controlling peripheral devices.

The sbRIO-9606 offers a -40 to 70 °C operating temperature range along with a 9 to 30 VDC power supply input range. It provides 256 MB of dynamic random access memory (DRAM) for embedded operation and 512 MB of nonvolatile memory for storing programs and data logging. The sbRIO-9606, together with NI 9683 GPIC board, is designed to be easily embedded in high-volume power electronics control applications.

Related Links:
NI Single-Board RIO Embedded Control and Acquisition

FPGA Advantage

By taking advantage of the user-configurable Spartan-6 FPGA, you can develop your power electronics control application faster and with a smaller budget. The LabVIEW toolchain, combined with a Spartan-6 FPGA and a complete set of I/O for power electronics, offers many advantages versus traditional digital signal processors (DSPs).

1. Reconfigurability
At the highest level, FPGAs are reprogrammable silicon boards containing a matrix of reconfigurable gate-array logic circuitry. Unlike DSPs, FPGAs are not constrained by a specific set of instructions or hardwired processing units. Using prebuilt logic blocks and programmable routing resources, you can configure these boards for your specific power electronics control applications. In the past, implementing a DSP application (such as a PWM inverter control algorithm) on an FPGA typically took much more effort than implementing the same application on a DSP processor. It required familiarity with hardware description languages for programming the FPGA board. In addition, it required designing a custom I/O board to interface with the FPGA.

The NI Single-Board RIO GPIC addresses those challenges by providing an off-the-shelf board that you can program using the LabVIEW FPGA graphical environment to achieve all of the I/O you need for power electronics control. With LabVIEW FPGA graphical programming, you can define the logic in the FPGA board without knowledge of low-level hardware description languages (such as VHDL or Verilog) or board-level hardware design.

Figure 13. LabVIEW FPGA, Used for Designing an FPGA Board

Using LabVIEW FPGA, you can abstract the complexity of HDL programming and generate an FPGA implementation from a high-level graphical environment.

Figure 14. LabVIEW Analog I/O Implementation; FPGA Versus VHDL

With LabVIEW FPGA, you can integrate existing VHDL code, third-party IP, or IP cores from the Power Electronics IP Library into your LabVIEW FPGA application, so you can focus on application-specific features and code segments and use prebuilt cores for common tasks such as PWM, PID control, and Clarke and Park transforms.

The ability to import code and reconfigure the functionality of the FPGA is especially beneficial for smart grid applications from the perspective of long-term support, maintenance, and interoperability with evolving standards and communication protocols. The reconfigurable nature of the FPGA means you can achieve high performance, reduce application development time, and reuse code.

2. Performance
FPGAs have a highly parallel architecture, so they exceed DSP computing power. In fact, modern FPGAs contain dedicated DSP slices that are best-suited for typical DSP applications. Spartan-6 LX45 FPGAs have 58 dedicated, full-custom, low-power DSP slices to combine high speed with small size  while retaining system design flexibility.

Figure 15. Spartan-6 Versus a Generic DSP

When you compile your power electronics control application (custom, high-frequency digital PWMs) for an FPGA device, the result is a highly optimized silicon implementation that provides true parallel processing with the performance and reliability benefits of dedicated hardware circuitry. Because there is no OS on the FPGA board, the code is implemented in a way that ensures maximum performance and reliability.

In addition to offering high reliability, FPGA devices can perform deterministic closed-loop control at extremely fast loop rates. In most FPGA-based control applications, speed is limited by the sensors, actuators, and I/O modules, rather than FPGA processing performance. For example, the PID control algorithm included with the LabVIEW FPGA Module executes in just 300 ns (0.000000300 s).

FPGA-based control systems offer deterministic, closed-control performance at rates exceeding 1 MHz. In fact, many algorithms can be executed in a single cycle of the FPGA clock (40 MHz).

3. Cost and Time Savings
The highly parallel nature of FPGA data processing results in an order-of-magnitude increase in performance per dollar, compared to single-core DSPs. FPGAs also offer an increased performance per watt versus DSPs. FPGAs generally have a higher board-level power dissipation (DSPs typically consume 3 W to 4 W, and FPGAs, 7 W to 10 W); however, FPGAs can handle 40X the channel density of DSPs, resulting in much higher performance per watt.

Figure 16. The recent incorporation of minihardcore DSPs into the FPGA fabric has dramatically increased the performance of FPGAs, compared to single-core DSPs, as measured in multiply-accumulate operations per second.

On average, the performance per dollar of FPGAs doubles every 14 months. With an NI Single-Board RIO GPIC commercial off-the-shelf controller board, you can take advantage of FPGA performance and reliability with relatively low, nonrecurring engineering, compared to custom hardware design.

With the NI Single-Board RIO GPIC, you can significantly reduce the development time of your power electronics control application by taking advantage of the flexibility and rapid prototyping capabilities of the LabVIEW toolchain and the Spartan-6 FPGA. After testing your controller design in the LabVIEW FPGA and Multisim co-simulation environment, you can deploy the same code onto the FPGA and test it with physical I/O. You can then implement incremental changes and use the reconfigurability of the FPGA to iterate on the final design.

Related Links:
NI Single-Board RIO Embedded Control and Acquisition

Introduction to FPGA Technology: Top 5 Benefits

Spartan-6 Family Overview

Real-Time Simulation Tools

Using the NI Single-Board RIO GPIC, you can perform HIL simulation to reduce the cost of field testing and prototype development. You can deploy the system model (state-space model or JMAG finite element analysis (FEA) software model) to a number of off-the-shelf real-time targets such as NI CompactRIO and NI PXI. These hardware targets combine an embedded processor with a real-time OS and a user-configurable FPGA so your code can execute with hard real-time performance. With cycle times in the hundreds of nanoseconds and low jitter, you can accurately simulate the I/O behavior of the physical system and verify controller performance.

With HIL testing, you can develop the software and hardware components of your system in parallel, reducing overall development time. For example, with electric motor system development, the electric motor and its engine control unit software can be developed simultaneously, so the majority of errors in the embedded software are corrected when motor development is complete.

Figure 17. NI cRIO-9082 as an HIL Simulator

Electric motor control signals typically operate in the range of 20 kHz to 25 kHz. To accurately simulate the electric motor, the time steps of the electric motor model must be at least 10X smaller than the period of the control signal. This means that the loop rates of electric motor simulators must be able to run at a minimum of 200 kHz, which is dramatically faster than a traditional HIL system. Figure 18 illustrates the importance of fast simulation loop rates.

Figure 18. Electric Motor HIL Simulation at Various Loop Rates

FPGA technology naturally fits in high-speed, real-time applications. All FPGA-based processing takes place inline and independently of the system CPU. This results in extremely low latency and high-speed signal processing for accurate physical I/O simulation.

With FPGA technology, you can tune and increase controller design efficiency so you can import nonlinear FEA models of your unit under test (UUT) for high-fidelity HIL simulation. This capability is provided by the JMAG-RT Add-On for NI VeriStand software.

Figure 19. Electric Motor HIL Simulation

Using the JMAG simulation software and the JMAG-RT Add-On, you can generate a .RTT file to create the FPGA personality that runs in real time. The JMAG-RT Add-On generates a lookup table that contains the parameters of your UUT (here, a motor) that are used to collectively characterize your device and accurately capture its nonlinear behavior.

Figure 20. FEA Model Implementation on the FPGA

Once the lookup table is generated, the model converter function reads the .RTT file and the lookup table, and sends the data to the NI RIO FPGA module, where the data is converted to fixed-point and loaded into onboard DRAM. Once the lookup table is loaded into DRAM, values are continuously polled from the table based on the current state of the model to create the nonlinear effects associated with the UUT.

Related Links:
High-Performance Electric Motor Simulation Using NI VeriStand and JMAG-RT
NI and JSOL/JMAG Announce New Tools for ~1 MHz FEA-Based Real-Time FPGA Simulation of PMSM Motor/Generator, Inverter, and Load

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4. Next Steps

Order the NI Single-Board RIO GPIC Evaluation Kit

View and share resources in the Power Electronics Development Community

Read customer success stories

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