Waveform Acquisition and Logging on CompactRIO Sample Project Documentation

The Waveform Acquisition and Logging on CompactRIO sample project acquires continuous waveform data and logs it to disk on the real-time controller. The acquisition code, which was created with the LabVIEW FPGA Module, runs on the FPGA inside the CompactRIO device.

1. Developer Walkthrough
2. Features
3. Basis
4. System Requirements
5. Overview
6. Running this Sample Project
7. Adapting this Sample Project to Your Hardware

Developer Walkthrough

See a developer walkthrough of the RIO sample projects.

Features

• Headless operation with optional user interface—The user interface VI interacts with the CompactRIO device and displays data. This VI can connect and disconnect from the device at any time without affecting the acquisition and logging loop.
• Triggered data logging—The real-time VI logs acquired data to disk as TDMS files when a trigger condition is met. This sample project also manages the amount of disk space being used.
• Error handling—The application reports and logs all errors from the CompactRIO device, shutting down on any critical error.

Basis

This sample project is based on the Simple State Machine and Queued Message Handler templates. Refer to the Simple State Machine and Queued Message Handler templates and their documentation, available from the Create Project dialog box, for information about how these templates work.

System Requirements

Development System

• LabVIEW Full or Professional Development System
• LabVIEW FPGA Module
• LabVIEW Real-Time Module
• NI-RIO device driver software

NI CompactRIO Device in FPGA Interface Mode

This sample project is designed for an NI cRIO-9074 with the following components:

• Software:
  • LabVIEW Real-Time
  • Network Streams
  • Network Variable Engine
  • NI System Configuration
  • NI-RIO
  • NI-Watchdog
• NI C Series accelerometer/microphone input module. This sample project is designed to read four channels of input from an NI 9234 module in slot 1.

Overview

This sample project consists of nine parallel loops across three execution targets. The following loops run in parallel on the desktop computer:

• Handling events from the user interface (UI Main.vi - Event Handling Loop)—Produces messages to the UI Message Loop based on front panel events.
• Handling messages from the user interface and the real-time controller (UI Main.vi - UI Message Loop)—Receives and responds to messages from the Event Handling Loop and, using network streams, the RT Message Handling Loop.
• Displaying messages and data from the CompactRIO device (UI Main.vi - Monitoring Loop)—Displays the latest values of information acquired from RT Loop - System Health and FPGA Monitoring.vi.

The following loops run in parallel on the real-time controller:

• Handling commands from the user interface (RT Loop - UI Commands.vi)—Reads commands that are sent from UI Main.vi on the development computer and produces the appropriate messages.
• Handling messages from all loops on the real-time controller (RT Main.vi - Message Handling Loop)—Consumes messages from all loops that run on the real-time controller.
• Ensuring the RT controller remains responsive (RT Loop - Watchdog.vi)—Pets the watchdog, ensuring the RT controller remains responsive.
• Monitoring diagnostic information from the real-time controller and data from the FPGA (RT Loop - System Health and FPGA Monitoring.vi)—Monitors CPU and memory usage of the real-time controller and data from the FPGA VI. This information is written to network-published shared variables and appears on the System Monitoring tab of UI Main.vi.
• Acquiring and logging data from the FPGA (RT Loop - Acquisition and Logging.vi)—Runs FPGA Main.vi, reads data from the DMA FIFO, and logs this data to disk.

The following loop runs on the FPGA:

• Acquiring data (FPGA Main.vi - Acquisition Loop)—Acquires data from the C Series module inputs and writes this data to a DMA FIFO.

Running this Sample Project

1. Adapt the sample project to your hardware.
2. In the Project Explorer window, open My Computer»Utility - Configuration File Generator.vi.
3. Enter the configuration values that are appropriate for your application. Be sure to look at all the values in the TDMS Properties array.
4. Run the VI. LabVIEW generates a configuration file, Config.xml in the same directory as the .lvproj file.
5. Transfer this XML file to the root folder of the real-time controller.
6. Run RT CompactRIO Target»RT Main.vi. This VI begins acquiring data and logging it using the configuration settings in Config.xml.
7. Open and run My Computer»UI Main.vi.
8. Enter the IP address of the CompactRIO device in the Controller Address text box and click Connect.
9. After you are connected, display live data in the waveform chart by clicking Acquire Live Data. Change the Live Data Channel control to see live data from different channels.
10. Click Exit to exit the application.

Adapting this Sample Project to Your Hardware

The FPGA VI in this sample project is compiled for specific FPGA and I/O hardware. If you have a different FPGA or different C Series modules, you must adapt this sample project to your hardware. The following steps refer to NI CompactRIO devices, but you also can adapt this sample project to an NI Single-Board RIO device.

1. Ensure all devices are configured and connected to the same network as the development computer.
2. In the Project Explorer window, add or discover your RT CompactRIO target to the top-level project item.
3. Add or discover your CompactRIO chassis to the RT Compact RIO target you added in the previous step. Ensure the chassis is set to LabVIEW FPGA Interface mode.
4. Add or discover your FPGA target to the CompactRIO chassis you added in the previous step. When prompted to deploy settings, click Deploy Later.
5. Add or discover your C Series input module to the FPGA target you added in the previous step.
6. Drag the following project items from the default RT CompactRIO target to the one you added in step 2:
   • Error Handlers folder
   • Globals folder
   • Support VIs folder
   • RT Loops folder
   • Type Definitions folder
   • Shared Variables.lvlib
   • RT Main.vi
7. Drag the following project items from the default FPGA target to the one you added in step 4:
   • Support VIs folder
   • Type Definitions folder
   • FPGA Main.vi
8. Delete the default RT CompactRIO Target project item that no longer has any VIs associated with it.
9. Re-establish the link between RT Main.vi and the bitfile:
   1. Open Start Acquisition and Logging.vi, located in the Support VIs folder on the RT CompactRIO Target.
   2. Drag FPGA Main.vi from the Project Explorer window to the Open FPGA VI Reference VI function.
10. Open FPGA Main.vi and ensure the FPGA I/O Node uses the input channels you want. For example, you may want the FPGA I/O Node to read from Mod2/AI5 instead of Mod1/AI2. The actual channels you read from depend on your application.
    
    By default, the FPGA I/O Node in this VI reads from Mod1/AI0–3.

You now can compile the FPGA VI and run it as part of your application.

Configuring Sample Project Settings

In the Project Explorer window, open My Computer»Globals»Global - Configuration Options.vi and configure the sample project settings.

Copyright

© 2012 National Instruments. All rights reserved.

For copyright notices, conditions, and disclaimers, including information regarding certain third-party components used in LabVIEW, refer to the Copyright topic of the LabVIEW Help.

Trademarks

LabVIEW, National Instruments, NI, ni.com, LabVIEW, the National Instruments corporate logo, and the Eagle logo are trademarks of National Instruments Corporation. Refer to the Trademark Information at ni.com/trademarks for other National Instruments trademarks.

Patents

For patents covering the National Instruments products/technology, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents.

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