Get Better System Performance and Resource Utilization Through LabVIEW FPGA IP Builder

LabVIEW FPGA IP Builder is an add-on to LabVIEW FPGA that you can use to easily generate high-performance FPGA IP by combining high-level synthesis (HLS) technology with the power of LabVIEW and NI FPGA-based hardware. This white paper covers the basic principles of LabVIEW FPGA IP Builder and provides examples of how you can use it to obtain better results.

1. Introduction to LabVIEW FPGA IP Builder
2. LabVIEW FPGA IP Builder Principles
3. Using LabVIEW FPGA IP Builder
4. Hardware Support
5. Try LabVIEW FPGA IP Builder

Introduction to LabVIEW FPGA IP Builder

Field-programmable gate array (FPGA) devices offer a powerful platform for embedded development by combining the flexibility of software-based reconfiguration with hardware reliability and determinism. While the NI LabVIEW FPGA Module abstracts many of the inherit complexities inherent in digital circuitry design, you must still master several advanced optimization concepts if you wish to push FPGAs to the limits of their capacity or performance. Advances in synthesis research are enabling a new type of tool with which you can obtain better quality results without needing advanced optimization techniques.

LabVIEW FPGA IP Builder is an add-on to LabVIEW FPGA that you can use to easily generate high-perform ance FPGA IP by combining high-level synthesis (HLS) technology with the power of LabVIEW and NI FPGA-based hardware. With this add-on, you can use a LabVIEW diagram to generate multiple implementations of the same algorithm with different performance characteristics based on directives specified separately from the code. Because these directives are stored separately from the code, you can easily explore design trade-offs and reuse your IP to meet multiple design constraints without having to modify it and reverify it.

LabVIEW FPGA IP Builder is useful when your desired algorithm or processing function is not already available from the different IP sources in the LabVIEW FPGA ecosystem, or whenever the available IP does not meet your performance or resource-utilization constraints. In this case, it can help you achieve success and increase productivity, regardless of whether you are tackling your first FPGA project or you are already an advanced LabVIEW FPGA user. If you are venturing into more demanding FPGA applications, you can take advantage of LabVIEW FPGA IP Builder to generate algorithms with performance comparable to that of hand-optimized single-cycle Timed Loop (SCTL) code. Advanced LabVIEW FPGA users, already familiar with SCTL optimization techniques, can use this add-on to improve the reusability of their existing IP with little effort beyond specifying new performance goals through design directives. 

LabVIEW FPGA IP Builder features HLS technology from Xilinx to help you compile and optimize algorithms written in LabVIEW. You can use HLS technology to generate an efficient hardware design from three main components:

1. An algorithm, implemented in a high-level language such as LabVIEW
2. Synthesis directives, specifying the performance and resource objectives
3. An FPGA target with known characteristics

Figure 1. Based on design directives for a specific target platform, high-level synthesis technology generates efficient HDL implementations of an algorithm implemented in a high-level language.

The output of an HLS tool is typically an equivalent implementation of the original algorithm in a hardware description language (HDL) such as VHDL or Verilog.

The separation between directives and high-level design means that optimization no longer requires changes to the code. With LabVIEW FPGA, you may start with an algorithm similar to the filter below:

Figure 2. Original FIR Filter Algorithm Implementation

If you need to optimize such a filter to achieve higher throughput, you must manually unroll the loop and be explicit about parallelization, which produces something similar to the diagram below.

Figure 3. Equivalent FIR Filter Implementation Optimized for FPGA Use Inside a Single-Cycle Timed Loop (SCTL)

With LabVIEW FPGA IP Builder, you can achieve comparable performance by simply feeding the tool the diagram below and specifying design directives to meet your needs. This version of the code is still very similar to the original algorithm, so readability and maintainability are preserved.

Figure 4. Equivalent Implementation of the FIR Filter to Be Consumed by LabVIEW FPGA IP Builder

The first thing you notice when using the LabVIEW FPGA IP Builder is its presence under your LabVIEW FPGA Target item in the LabVIEW project. Under that item, you can add and work on your algorithms as regular VIs. You store and specify directives as separate project items, and you can associate multiple directives with the same VI. The VI under the IP Builder item, which contains your algorithm, the directives item, and the FPGA target model, provide LabVIEW FPGA IP Builder with all the information it needs to analyze and compile your code to meet your design goals.

Figure 5. Sample View of LabVIEW Project With IP Builder Item as Parent of VI and Directives Items

The direct result of this separation of code and directives is that you do not have to change your code to optimize it for performance or resource utilization as long as LabVIEW FPGA IP Builder can do it for you. A more subtle benefit of this separation is the fact that you can then reuse your existing IP for multiple projects through the application of different design directives.

Figure 6. With LabVIEW FPGA IP Builder, you can reuse your IP to meet multiple design challenges through the use of different directives.

The LabVIEW FPGA IP Builder Directives dialog helps you generate estimates of the generated code’s performance. You can obtain these estimates much faster than the time it takes to compile the FPGA design, so you can quickly iterate on your design using those reported as feedback.

The typical process of creating IP with LabVIEW FPGA IP Builder involves a sequence of straightforward steps. A few iterations may be required if the tool cannot satisfy all of your design directives, but the process is usually quick thanks to relatively fast estimations. This section reviews the typical tool flow, from algorithm creation or adaptation to the insertion of the generated output in the overall design.

Figure 7. Typical LabVIEW FPGA IP Builder Design Flow

An important objective of LabVIEW FPGA IP Builder is to help you reuse existing LabVIEW IP to implement high-performance FPGA-based applications. You should be able to start with an existing implementation of the desired IP and add a copy of the VI under the IP Builder item in the project. If you don’t already have this IP, you can create it using regular LabVIEW syntax outside the SCTL. Some caveats do exist due to the constraints of FPGA technology and limited support for functions and data types, so you may have to slightly tweak algorithms to satisfy some basic tool requirements. Consider the following when developing IP with the LabVIEW FPGA IP Builder:

• Limited data-type support: Floating-point data types such as double or single precision are not supported in LabVIEW FPGA IP Builder, so you must implement all code sections that require this support using fixed-point data types. Be careful when performing this conversion because integer and fixed-point word length can have a negative effect on performance and resource utilization. The product documentation contains an exact list of which data types are supported.
• Arrays must feature a fixed size and their branches must be minimized: The limited nature of FPGA resources means that data structures need to be bounded in size, and their propagation through the diagram needs to be considered carefully to prevent the need for additional buffers to handle copies. The product documentation contains helpful tips on how to manage resource utilization and promote efficient access to array data structures.
• Limited function support: LabVIEW FPGA IP Builder works with a limited set of operations that cover basic logical and arithmetic operations as well as basic flow control constructs. If a required function is missing, you often can build it from these more fundamental constructs. Some of the shipping examples show how to build operations such as square root, sine/cosine, and vector-scalar product. Function support will increase with future versions of the product. The product documentation contains an exact list of supported functions.

Once you implement the algorithm, you can execute it under the LabVIEW FPGA IP Builder context. You can therefore write test benches around the code to verify its behavior. Once you are satisfied with the functional behavior of the code, you can proceed to create directives that suit your application.

You can create one or more sets of directives for a given VI under the IP Builder item in the LabVIEW project. Directives are stored as part of your project and are defined through a configuration dialog. The Directives tab of the configuration dialog contains a screenshot as well as a tree-based representation of the diagram associated with the directives item. The tab also features a context-sensitive table of directives that you can apply to the currently selected diagram item. The top-level item is initially selected by default, so the directives shown in that table apply to the overall diagram. If you select specific items from the tree view, the table is updated to reflect the directives that apply to the selected element. You can enable or disable the individual directives and assign values to them when appropriate.

Figure 8. With the Directives dialog, you can associate design constraints with parts of your diagram.

Once you have set the directives as required by your design, you can switch over to the Estimates tab to find a tree view representation of the diagram elements annotated with the desired directives that apply to them. Use the button on the right-hand side of the page to start and view the estimation process with a configurable display that shows the tool log as it estimates the achievable performance and resource utilization. The estimation process usually takes a couple of minutes but can vary depending on the size of the diagram and the complexity of the problem imposed by the design directives. Once the process is finished, you can see performance and resource utilization reports on the same window.

Figure 9. LabVIEW FPGA IP Builder provides performance and resource estimates in a fraction of the time it takes to compile a design.

The process of setting directives and estimating design characteristics can become iterative because you typically have a trade-off between the different directives. Additionally, certain directives tend to take precedence over others, so you may need to make a few attempts to strike the right balance. The LabVIEW FPGA IP Builder product documentation provides a suggested flowchart for configuring directives based on whether the performance and resource utilization goals are being met. The following section walks through an example of how you can use directives to achieve different goals.

You can use most of the directives in LabVIEW FPGA IP Builder to specify the performance characteristics of the algorithm. Throughput, latency, and resource utilization are the most common design factors in high-performance applications, and they tend to be mutually exclusive.

Throughput is the direct result of two factors: the speed of the clock you are using to drive your design and how many cycles are required before your algorithm can accept new inputs. The number of cycles required before the algorithm can accept new inputs is also referred to as the initiation interval (II). Design throughput can therefore be defined as

where samples per iteration is the number of data samples consumed by each call to your algorithm, which is a fixed characteristic of your design. You can, for example, implement a parallel version of an algorithm that processes multiple samples per call.

You can use the FIR filter example that is shipped with LabVIEW FPGA IP Builder to learn how to increase throughput with directives. Out of the box, the default directive for the VI uses a clock rate of 40 MHz and an unspecified initiation interval. Figure 10 shows the initial estimate results for that specific directive configuration.

Figure 10. Default Directive Settings for FIR Filter Example

This initial estimate shows that the tool can achieve the requested clock rate at an initiation interval of 62 cycles. You can then specify a much higher clock rate, 200 MHz, through the value of the clock rate directive. Figure 11 shows the directive settings and the results.

Figure 11. Estimates indicate that the design can surpass the requested clock rate with an increased initiation interval and slightly higher resource utilization.

The estimate shows that the tool is confident about the requested clock rate. Resource utilization barely goes up, and the higher clock rate is accompanied by a 15-cycle increase in the initiation interval. You can then force the initiation interval to have a value of 1 to achieve the best possible throughput at the specified clock rate. Figure 12 shows the directive settings and their corresponding estimated results.

Figure 12. Forcing the initiation interval yields higher throughput at the cost of increased resource utilization.

The tool estimates indicate that it can meet the desired clock rate and initiation interval at the cost of higher resource utilization. You can use the LabVIEW FPGA IP Builder to apply pipelining and parallelization techniques to try to meet more aggressive timing constraints. Keep in mind that those techniques use more FPGA resources.

Table 1 summarizes the requested and achieved performance and resource utilization for the three configurations. Notice how throughput is substantially increased by specifying a higher clock rate and smaller initiation interval. For the third set of directives, the tool estimates that the generated filter can achieve a throughput of 250 million samples per second. The whole iterative estimation process took only a few minutes and resulted in a throughput increase of several orders of magnitude without code modifications.

Table 1. This summary of directive settings and estimated results shows you can achieve higher throughput by increasing clock rate and reducing the initiation interval, though at the cost of higher resource utilization.

Keep in mind that using IP that exceeds the performance requirements of your application usually means you are paying a higher resource cost, so the “right” directives for a given application are not necessarily the ones that yield the highest throughput. Instead, they are the ones that meet your design requirements in the most efficient manner. Therefore, you can imagine using the first set of directives for applications where a throughput of 680 kS/s is adequate instead of using the best performing IP at a higher resource cost. Without HLS technology, you have to maintain a discrete number of algorithm implementations to serve multiple points of the requirement spectrum, which leads to poor reuse and increased development time. With LabVIEW FPGA IP Builder, you can easily explore the continuum of performance and resource utilization for a given algorithm, which makes it a powerful tool.

Once you are satisfied with the estimates for a given algorithm and directive set, you can proceed to generate the design by creating and building a new build specification. You can create one or more build specifications per directive item in your project.

LabVIEW FPGA IP Builder build specifications are similar to build specifications found elsewhere in the LabVIEW development experience. You can specify the desired directive set as well as the name and location of your output file. You also can add comments to the build specification for documentation purposes.

After you have completed the build specification, LabVIEW FPGA IP Builder generates the desired HDL implementation of the algorithm, wraps it in an IP Integration Node, and drops that node inside a new VI with the desired name. The generated VIs then appear inside your project hierarchy in an appropriately named virtual project folder. This represents a good point for further validation and verification of the generated VI. You can run the FPGA IP to validate its functionality, initiation interval, and latency. You also can validate the clock rate and resource usage by including the FPGA IP in an SCTL and generating a compilation report. Refer to the “Validating Generated FPGA IP” topic of the product documentation for more information on how to accomplish these tasks.

Once you are sure that the generated VIs meet your needs, you can place them in an SCTL and integrate them with the rest of your application. You must use IP generated by LabVIEW FPGA IP Builder inside the SCTL. The most important part of this integration process is wiring the handshaking signals so that the generated IP can consume data when appropriate and communicate to nodes immediately downstream when its output is valid and ready for consumption.

Figure 13. The generated IP is wrapped in an IP Integration Node and placed inside a VI that you can use within a single-cycle Timed Loop in your application.

Once you have integrated the IP into your design, you can compile it. If the compilation step succeeds, the generated IP can function at the required rates. At this point, you can validate that the application works by running the necessary system-level tests.

The LabVIEW FPGA IP Builder currently supports a limited set of hardware targets. Refer to the latest product release notes for a list of supported hardware.

National Instruments is committed to making it easier for engineers and scientists to harness the power of FPGA-based devices. LabVIEW FPGA IP Builder takes advantage of the latest HLS technology from Xilinx so you can create high-performance IP that you can easily reuse to meet a variety of design challenges. You may want to use LabVIEW FPGA IP Builder when the existing IP resources do not satisfy your functional, performance, or resource requirements.

If you think you can benefit from using the LabVIEW FPGA IP Builder to build FPGA-based applications, you can download and evaluate it for a limited period.

To learn more about the product, see the online documentation and latest release notes.

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Reader Comments | Submit a comment »

when i take a look on figure 2 (the starting point) then i think the best hand optimized code is y=0 I assume, never was the code so realized like the code in figures 2 and 3. I have no knowledge over filter design, but i'm familiar with LabView and LabView FPGA. It is very unfortunate that nobody hasn't reviewed this article.
- s.ey@lmtb.de - Oct 19, 2012