LabVIEW FPGA 2012 Productivity Enhancements and Optimizations

LabVIEW FPGA enables designers to use less engineering resources and get to market faster than with other FPGA design tools. With LabVIEW FPGA 2012, we’ve made further improvements to help you get to market even faster. NI LabVIEW FPGA 2012 offers powerful new features for shortening your development time and improving the performance of your applications. This document highlights some of the top new features in LabVIEW FPGA 2012.

1. Proven, NI Recommended Architectures for Control and Monitoring Applications
2. Better Verification of FPGA VI with Execution on Development Computer
3. Floating-Point Support within LabVIEW FPGA
4. Array and cluster support within Single-Cycle Timed Loops
5. Faster Compilations with Support for Linux
6. Higher Clock Rates with Single Cycle Timed Loops
7. Array Support with High-Throughput Math Nodes
8. New Tools for Simplifying IP Reuse
9. FIFO Improvements for Faster Streaming
10. Improved Ability to Create Reusable SubVIs

Proven, NI Recommended Architectures for Control and Monitoring Applications

For LabVIEW applications based on NI CompactRIO / Single-Board RIO hardware, the new LabVIEW Project Templates and Sample Projects provide applications and source code that are designed to scale to a wide variety of control and monitoring applications.

Figure 1. LabVIEW 2012 Sample Projects provide proven, reliable architecture starting points for embedded control and monitoring applications

If you’re starting a new application, the Sample Projects provide a starting point that can shorten your development time and ensure that your design is reliable. If you have an existing LabVIEW RIO application that you would like to optimize or improve, you can leverage the Sample Projects to learn LabVIEW FPGA design techniques and architectural best practices that are specific to embedded applications. For more information on LabVIEW Sample Projects for control and monitoring applications, see the LabVIEW Real-Time 2012 Sample Projects Webcast and the LabVIEW Templates and Sample Projects whitepaper.

Better Verification of FPGA VI with Execution on Development Computer

Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by running the FPGA VI on a development computer with simulated I/O. When you run the FPGA VI on the development computer, you can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. In LabVIEW FPGA 2012, when you run your FPGA VI on your development PC, you will notice improved fidelity with respect to time when executing multiple Single-Cycle Timed Loops at same or different clock rates, and when sharing resources between two or more Single-Cycle Timed Loops.

Figure 2. Improved fidelity when executing FPGA VI on development computer

Floating-Point Support within LabVIEW FPGA

Previous versions of LabVIEW FPGA required developers to use the fixed-point data type when fractional data was needed. While the fixed-point data type is very efficient for hardware-based designs when it comes to speed and resource utilization, it does not provide the flexibility that the floating-point data type offers. In LabVIEW FPGA 2012, the single-precision floating-point data type is natively supported. Not only will this enable users to directly retrieve floating-point data from DMA FIFOs, avoiding an expensive conversion from fixed-point to floating-point on the real-time or windows host, but it will enable DSP designers to solve linear-algebra problems in LabVIEW FPGA that require a wider dynamic range that what fixed-point or integer type data provide. It is important to note that while the floating-point data type offers many benefits, it has limited support when used in Single-Cycle Timed Loops, and uses significantly more FPGA resources than the fixed-point data type for certain operations.

Figure 3. Floating point data type support in LabVIEW FPGA 2012

For more information on the functions and structures that support the floating point datatype, see the LabVIEW FPGA 2012 Help document Functions that Support the Single Precision Floating-Point Data Type in FPGA VIs. For benchmarks that compare floating-point datatype resource utilization to fixed-point, see the whitepaper LabVIEW FPGA Floating Point Data Type Support.

Array and cluster support within Single-Cycle Timed Loops

In LabVIEW FPGA 2012, boolean, numeric, and comparison operations within single-cycle timed loops now support cluster and array data types. Each primitive operation is parallelized on the FPGA for maximum performance, so you no longer need to break out each operation individually. This idea was originated from the LabVIEW FPGA Idea Exchange.

Figure 4. Cluster and array data type support added to single-cycle timed loops

Faster Compilations with Support for Linux

When it’s time to compile your LabVIEW FPGA VI, you can iterate faster with new Linux-based FPGA compilation options. Linux-based compilation workers offer substantial performance benefits over Windows-based workers. For large, complex FPGA VIs, NI has seen a significant decrease in compilation times. The performance gains vary based on the specifications of the machine performing the compilation and the size of the FPGA target. Linux-based compilation is available with the LabVIEW FPGA Compile Compile Cloud Service, in addition to remote PC compile works and the NI Compile Farm Toolkit. For more information on using Linux machines as a compile worker with LabVIEW FPGA 2012, see the NI LabVIEW FPGA Compilation Options whitepaper and the FPGA Compile Worker Performance Benchmarks whitepaper.

Figure 5: Linux-Based FPGA Compilation Options

Higher Clock Rates with Single Cycle Timed Loops

In order to compile Single-Cycle Timed Loops at higher clock rates for very large streaming applications, the compiler, under certain conditions, can remove enable chain for the Single-Cycle Timed Loops that have no dataflow dependences. Removing this enable chain will decrease routing congestion and improve timing performance. For more information on how to leverage this new feature, see the LabVIEW FPGA 2012 Help document Improving Timing Performance in Large FPGA VIs. 

Array Support with High-Throughput Math Nodes

When designing sophisticated DSP algorithms for high-throughput applications, there is often a need to perform high-throughput math on arrays. In LabVIEW FPGA 2012, the High-Throughput Math Nodes support fixed-size array inputs, eliminating the need to perform math operations element-by-element with multiple nodes.

Figure 6: Array Support for High-Throughput Math Functions

New Tools for Simplifying IP Reuse

When designing LabVIEW FPGA algorithms, it’s important to be able to re-use the IP that was created for one application within another. Often times, developers find themselves modifying the algorithm they created, so that they FPGA VI will compile in a way that it meets system requirements, such as execution speed, throughput, or latency. When they want to reuse this algorithm for another application with different system requirements, they are required to make major modifications to the LabVIEW FPGA source code. LabVIEW FPGA IP Builder is an add-on tool to LabVIEW FPGA , that enables developers to write one algorithm that can be easily compiled for multiple systems for various system requirements, without modifying the source code. For more information on LabVIEW FPGA IP Builder, see the whitepaper Get Better Performance and Resource Utilization with LabVIEW FPGA IP Builder.

Figure 7: LabVIEW FPGA IP Builder enables users to design an algorithm in LabVIEW, and compile it for multiple applications with different performance requirements

FIFO Improvements for Faster Streaming

LabVIEW FPGA 2012 includes several new features that enable improved streaming performance with FIFOs for PXIe FlexRIO targets. One example is a deeper and wider DMA FIFO. The depth of a DMA FIFO has been increased from 32k samples to 256k samples, making it easier to achieve sustainable rates when streaming data at very high rates.

Additional improvements to both the DMA FIFO and Peer-to-Peer FIFO enable users to pack small data sizes elements into a 64-bit array before sending to a host. With this new feature users can obtain higher transfer rates when transferring smaller data size elements between an FPGA target and host.  The number of elements that can be sent with a FIFO will depend on the datatype of the elements.

Figure 8: Write four 16-bit integers in parallel with DMA and Peer-to-Peer FIFOs for PXIe FlexRIO Targets

Improved Ability to Create Reusable SubVIs

You now have the option to use a new LabVIEW FPGA construct, the Register, to write light-weight, re-usable code for communication between loops executing in parallel.  You can think of the Register as a single-element Memory implemented with flip-flops.  Like globals, you can write and read Registers in the same or different clock domains.  Similar to FPGA I/O, Memories, FIFOs, and Clocks, Registers can be specified via name controls, which is how you write reusable subVIs with Registers.

Figure 9: Register functions are consistent with those for Memories and FIFOs

For more information on creating reusable subVIs with LabVIEW FPGA, see the NI LabVIEW FPGA 2012 Help Document Using Register Items in SubVIs. For more information on the Register, see the NI LabVIEW FPGA  Help Document Regsiter Items.

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