NI PXIe-5644R Vector Signal Transceiver Hardware Architecture

With the introduction of the NI PXIe-5644R vector signal transceiver (VST), National Instruments redefines instrumentation by bringing the flexibility of user-programmable FPGAs to RF instrumentation. 

1. High-Performance and Revolutionary Design
2. FPGA Basecard Architecture
3. Receiver Architecture
4. Transmitter Architecture
5. Synthesizer Local Oscillator (LO) Architecture
6. Calibration
7. Next Steps

High-Performance and Revolutionary Design

The NI PXIe-5644R VST combines RF I/O functionality typically found in vector signal analyzers (VSAs) and vector signal generators (VSGs) with NI or user-defined functionality for signal processing and control inside a field-programmable gate array (FPGA). The RF input and RF output have independent local oscillators (LOs), frequency coverage from 65 MHz to 6 GHz, and instantaneous bandwidth of up to 80 MHz. NI PXIe-5644R is a single 3-slot PXI Express module (see Figure 1 below). Multiple input, multiple output (MIMO) configurations can be created by using several VST modules in a single PXI Express chassis.

Figure 1: NI PXIe-5644R Hardware Front Panel

What’s so compelling about the NI PXIe-5644R? The high performance that is achievable in such a small footprint. Through advanced calibration and wideband digital correction, the NI PXIe-5644R VST can achieve the performance expectation of an R&D-grade instrument in an incredibly small form factor. This coupled with much faster test times and flexibility from the user-programmable FPGA makes the NI PXIe-5644R ideally situated for RF characterization, verification, validation, and production test.

While the high functionality and small footprint is impressive, the most revolutionary feature of the NI PXIe-5644R VST is the user-programmable Xilinx Virtex-6 FPGA, which is programmable with the LabVIEW FPGA Module. The FPGA is connected to the VSA and VSG baseband I/Q data, as well as 24 digital I/O lines with a data rate of up to 250 Mbit/s. This powerful combination of RF, high-speed digital I/O, and FPGA technologies gives NI PXIe-5644R the ability to address a wide variety of applications such as real-time device under test (DUT) control, custom triggering, power-level servoing, software defined radio, channel emulation, and many others.

FPGA Basecard Architecture

The NI PXIe-5644R FPGA basecard consists of a Xilinx Virtex-6 FPGA, baseband clocking circuitry, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), a programmable function digital I/O line (PFI 0), digital I/O connector, PCI Express interface, PXI triggers, DRAM, and SRAM.

Figure 2: Block Diagram of the NI PXIe-5644R FPGA Basecard

Xilinx Virtex-6 FPGA

The NI PXIe-5644R contains a Xilinx Virtex-6 LX195T FPGA, which is used for system configuration, digital data movement, and digital signal processing. The FPGA has direct connections to the ADCs, DACs, PCI Express bus, DRAM, SRAM, PFI 0, digital I/O, and PXI triggers, allowing for custom programming to meet the needs of many types of applications.

Reconfigurable FPGA Resources

The Xilinx Virtex-6 LX195T FPGA has the following resources.

Programmable Using LabVIEW FPGA

The Xilinx FPGA on the NI PXIe-5644R is fully programmable using the LabVIEW FPGA Module. LabVIEW is well suited for FPGA programming because it clearly represents parallelism and data flow, so users who are both experienced and inexperienced in traditional FPGA design can productively apply the power of reconfigurable hardware.

National Instruments provides LabVIEW sample projects and Instrument Design VIs for the NI PXIe-5644R that allow users to get up and running quickly with their first measurement. The Instrument Design VIs provide the user access to modify LabVIEW code at both the FPGA and processor levels (for example, PC and real-time OS), and are categorized according to function, such as configuration, acquisition, generation, digital signal processing (DSP), and synchronization (see Figure 3 below). To learn more about the software of the NI PXIe-5644R VST, read the VST Software Architecture white paper or watch the VST webcast.

Figure 3: LabVIEW Sample Project and Instrument Design VI Mapping to NI PXIe-5644R Hardware

Baseband Clocking

The NI PXIe-5644R has multiple clocks inside the FPGA. The main clock is the sample clock, which is used to clock the ADCs, DACs, and the related FPGA logic.

Sample Clock

The sample clock runs at 120 MHz and is exported by the phase-locked loop (PLL). You can select the internal TCXO, NI 5644R REF IN front panel connector, or PXI_CLK 10 as the reference signal for the PLL. The sample clock, in turn, is the reference signal for the RF IN and RF OUT internal LO circuits (see Figure 4 below). Although the sample clock frequency is fixed at 120 MHz, you can achieve high-resolution I/Q data rates using the Fractional Interpolation and Fractional Decimation DSP VIs inside the FPGA.

Figure 4: NI PXIe-5644R Clocking Architecture

FPGA Clocks

The following table lists the clocks in the FPGA. In addition to these clocks, LabVIEW FPGA allows for derived clocks at user-defined frequencies.

ADCs and DACs

The NI PXIe-5644R uses dual-channel, 16-bit ADCs and DACs. The ADCs and DACs are clocked at 120 MS/s to provide 80 MHz of complex bandwidth, and are automatically synchronized to the sample clock domain inside the FPGA. This conveniently allows for interfacing to both the ADCs and DACs in the same clock domain with full synchronization, which enables deterministic latency between receive and transmit. The RF IN and RF OUT IQ data streams are in the same clock domain in the FPGA. This makes programming easier by allowing for synchronization and deterministic latency for real-time test and embedded applications.

PFI 0

PFI 0 is a 3.3 v LVTTL, bidirectional, general-purpose digital I/O signal. The most common use of PFI 0 is as a trigger input or a marker/event output. However, because the PFI 0 I/O buffer is connected directly to the FPGA, its functionality can be programmed for custom applications using LabVIEW FPGA.

Digital I/O

The digital I/O on the NI PXIe-5644R is accessible via a VHCDI port. There are 24 bidirectional LVTTL digital I/O lines, configurable per port, with four lines per port (six ports total). The digital I/O connector also contains the Clock In and Clock Out lines, as well as PFI 1 and PFI 2 lines that can be used for triggering or as additional bidirectional digital I/O. Because the digital I/O buffers are connected directly to the FPGA, the functionality of the individual digital I/O signals can be programmed for custom applications using LabVIEW FPGA.

Cables and Accessories

National Instruments offers several cables and accessories that are compatible with the digital I/O connector. Note that these cables and accessories use a custom pinout that matches the NI PXIe-5644R digital I/O and maintain the 50 ohm transmission line environment. The use of other VHDCI cables is not recommended.

DRAM and SRAM

The NI PXIe-5644R has two banks of DRAM with 256 MB per bank and a theoretical maximum data rate of 2.1 GB/s per bank, and are each independently accessible from the FPGA. These DRAM banks are general purpose, but are often used for storing waveforms to be generated or waveforms that have been acquired. 

There is also 2 MB of onboard SRAM with a maximum read data rate of 40 MB/s and write data rate of 36 MB/s. SRAM is general purpose memory, which is often used for storing multiple hardware configurations that can be applied directly from the FPGA without intervention from the host.

PCI Express Interface

The NI PXIe-5644R has a PCI Express, Gen 1 x4 backplane connection, which is used for DMA transfers, programmed I/O, and peer-to-peer streaming.

Receiver Architecture

The NI PXIe-5644R features a homodyne RF receiver, also known as a synchrodyne, zero-IF, or direct-down conversion receiver. In a homodyne receiver, the incoming RF signal is fed into a frequency mixer just like in a traditional heterodyne receiver, such as the receivers found in the NI PXIe-5665 and NI PXIe-5663E VSAs. However unlike a heterodyne receiver, the frequency of the LO in a homodyne receiver is identical to, or very close to, the frequency of the incoming RF signal, resulting in a DC-centered or low IF signal such as 10 or 20 MHz.

The input signal is mixed down to baseband and split into in-phase (I) and quadrature-phase (Q) components, where the carrier is in-phase and offset by 90 degrees respectively. The I and Q path signals are then separately digitized resulting in I and Q data. Finally, the I and Q data streams are combined in software, rendering the original signal. Figure 5 shows a simplified block diagram of a homodyne, or zero-IF architecture.

Figure 5: Homodyne (Zero-IF) Architecture Basic Block Diagram

Homodyne (Zero-IF) Receiver Advantages

The homodyne architecture boasts a number of advantages over the traditional heterodyne architecture including simpler design, lower cost, less power consumption, and high selectivity, which allows separation of adjacent channels whose signals overlap. Other advantages include higher potential bandwidths, simpler designs with single LOs, and a smaller footprint due to a more compact design. These advantages are described in more detail below.

1.  Bandwidth. Receivers with single ADCs have a practical upper limit for signal bandwidth of 40 percent of the sample clock frequency. With the same sample clock frequency, homodyne architectures allow double the bandwidth, or 80 percent of the sample clock frequency, because two ADCs are used. In general, ADCs with lower allowable sample clock frequencies have better spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) performance. Homodyne receivers allow wider bandwidths without the trade-off in ADC performance that is a necessary trade-off of single ADC receivers.

2.  Single LO. With multichannel measurement systems becoming more important for multiple input, multiple output (MIMO) applications, sharing the LO is a requirement. With only one LO to share in a homodyne architecture as opposed to multiple LOs in a traditional heterodyne architecture, homodyne architectures become a more cost-effective and less complicated system to configure.

3.  Compact Design. Homodyne architectures have much simpler RF designs over heterodyne architectures. Fewer LO signals; no bulky, expensive RF and IF filters; and fewer conversion stages for the homodyne architecture make for a more compact design.

Homodyne (Zero-IF) Receiver Challenges

Although the advantages are numerous, the homodyne architecture does come with its own set of challenges, such as the inability to implement envelope detection. The NI PXIe-5644R overcomes this problem by using quadrature detection and digital signal processing.

DC offsets are another challenge of a zero-IF architecture. Any signal that mixes down to 0 Hz in the ZIF structure causes a spectral component at DC. This distortion falls at the center of the instantaneous bandwidth of the data acquisition. A spectrum composed of pasted together data acquisitions, each offset in frequency by the instantaneous bandwidth, will show this DC offset term replicated in the center of each data acquisition. Nulling of the DC offset is accomplished on the digitized I and Q data streams by applying offsets. A separate nulling procedure must be applied for each LO frequency, which is done automatically by running the NI PXIe-5644R self-calibration procedure.

Receiver Signal Path

The high-level architecture of the NI PXIe-5644R receiver design is shown in Figure 6. This diagram highlights the calibration synthesizer, optional attenuators for high power, optional amplifiers for low power signals, out of band select filters, additional gain and attenuation signal conditioning, and demodulation over one of three mixers depending on frequency.

Figure 6: NI PXIe-5644R Receiver Block Diagram

The select filter bank has eight different paths with lowpass or bandpass filters. These filters allow the receiver to filter out much of the unwanted noise, focusing only on the signal range of interest. After the select filtering and some additional signal conditioning, the RF signal is then sent to one of three demodulators, depending on frequency. Each demodulator operates within a specific band to optimize gain and phase.

The receiver path includes several solid state attenuators that provide more than 80 dB of attenuation, variable in 1 dB steps. The RF input is AC-coupled. There are three switchable gain amplifiers and a preamplifier to extend dynamic range and improve noise figure.

A low phase noise LO is supplied internally to connect multiple downconverters with a single LO source. Using the same LO source is useful for phase-coherent signal acquisition applications, such as multiple input, multiple output (MIMO) systems. When using this configuration, every NI PXIe-5644R RF channel sharing the common LO is tuned to the same RF frequency.

The downconverted baseband signal is directly transmitted to the internal ADC channels of NI PXIe-5644R. The ADC channels digitize the baseband analog signal at 120 MS/s over a 16-bit dynamic range and route the result to the onboard FPGA for further processing, and then transfer to the host.

Downconverter

The NI PXIe-5644R receiver features a single-stage, direct conversion (I/Q) downconverter. The RF signal is downconverted from the configured LO frequency to DC, where the baseband signal can be digitized for processing. This architecture allows for wide instantaneous bandwidth with high image suppression and minimal LO leakage. Image suppression and LO leakage performance is achieved by wideband quadrature correction. The receiver path is optimized to be used as a vector signal analyzer for wideband demodulation.

Low IF Mode and In-Band Retuning

A low IF receiver is another type of receiver that uses an IQ demodulator, where the block diagram is identical to the zero-IF receiver shown in Figure 5. Unlike in the zero-IF receiver where the LO frequency is positioned to be within the frequency range of the modulated signal, in the low IF receiver the LO frequency is placed outside of the modulated signal range. The result is that the DC component is no longer within the downconverted span. Many of the impairments associated with the DC term such as DC offset, 1/f noise, and in some cases baseband harmonics are no longer an issue.

You can combine the capabilities of LO tuning and digital frequency shifting to operate the NI PXIe-5644R in low IF mode. Acquiring or generating the signal of interest at a digitally shifted frequency from the carrier avoids the implications of LO leakage present in direct conversion topology. The trade-off is the maximum BW of the low IF receiver is half that of the zero-IF receiver given identical ADC sample rates. The NI PXIe-5644R supports up to 80 MHz of complex instantaneous bandwidth with an additional 4 MHz of complex bandwidth allocated for digital frequency correction. Additional frequency shift reduces the usable 80 MHz bandwidth to (80/2) - (x- 2) MHz, where x is the request digital frequency shift.

Transmitter Architecture

The RF transmitter architecture on the NI PXIe-5644R VST features two modulators, a filter bank, and additional signal conditioning. A high-level diagram is shown in Figure 7.

Figure 7: NI PXIe-5644R Transmitter Block Diagram

Transmitter Signal Path

The two modulators on the NI PXIe-5644R are the same ones that are used in the NI PXIe-5673E VSG.  They are optimized for phase and gain balance depending on frequency. The NI PXIe-5644R RF transmitter filter bank is the same one that is used in the RF receiver, featuring the same eight paths with lowpass or bandpass filters, as shown in Figure 7.

After filtering, the RF signal then enters the cascade signal conditioning stage, which comprises three programmable attenuators, one selectable amplifier, and two fixed amplifiers. Finally, the RF signal is switched to either the RF Out or Cal Out front panel connectors, depending on whether the transmit path is being calibrated.

Upconverter

The NI PXIe-5644R RF transmitter path features a single-stage, direct conversion (I/Q) upconverter, which upconverts the baseband signal from DC to RF at the configured LO frequency. This architecture allows for wide instantaneous bandwidth with high image suppression and minimal LO leakage. Image suppression and LO leakage performance is achieved by wideband quadrature correction. This path is optimized to be used as a CW generator or a VSG for wideband modulation.

The transmitter path includes four solid-state attenuators with more than 100 dB of attenuation, variable in 1 dB steps. An additional switchable gain amplifier is used when generating high-power signals.

A low-phase noise LO is supplied internally on the transmitter path, which is used to connect multiple upconverters with a single LO source. Using the same LO source is useful for phase-coherent signal generation applications, such as MIMO systems. When using this configuration, every NI PXIe-5644R RF channel sharing the common LO is tuned to the same RF frequency.

Considering Average Power and Crest Factor

Crest factor is the change in power between peak signal power and average root-mean-square (RMS) power. The crest factor for a sinusoid signal, as is used in CW mode, is 3 dB. In other words, the average RMS power of the sinusoid is 3 dB less than its peak power. For modulated signals, specifically OFDM, the crest factor can be much larger, in the order of 10 dB to 12 dB.

It is important to consider both the average RMS power and the crest factor of a signal when configuring the device for generation. The NI PXIe-5644R supports a maximum average power output power of 6 dBm, with support for up to a 12 dB crest factor. Beyond 6 dBm average power, the device is not guaranteed to be calibrated and linear. More importantly, if the average power is set to be higher power than 6 dBm and the crest factor of the signal is still 12 dB or more, severe saturation might occur or the reverse power protection circuitry of the NI PXIe-5644R may be enabled.

Synthesizer Local Oscillator (LO) Architecture

The NI PXIe-5644R features a frequency range of 65 MHz to 6 GHz with less than 1 Hz of tuning resolution. The tuning resolution combines LO step size capability and frequency shift DSP implemented on the FPGA.

There are two LO stepping modes:

1. Integer stepping mode with 4, 12, and 24 MHz steps
2. Fractional stepping mode with 200 KHz steps. This mode has more granularities but also has more spurs. This is the mode where specifications are guaranteed.

The NI PXIe-5644R synthesizer LO begins with a 120 MHz clock into a PLL with three vector-controlled oscillators (VCOs) at frequencies 2 to 2.5 GHz, 2.5 to 3 GHz, and 3 to 4 GHz. If the desired output signal is less than 4 GHz, then the current signal is switched into a divider. Likewise, if the desired end signal is 4 to 6 GHz, then the current signal is switched into a doubler (x2 multiplier). This stage is followed by a filter bank with additional dividers to remove harmonics if necessary.

After some gain is applied, the signal is then switched to either an internal or external oscillator, the latter being for applications requiring phase-coherent MIMO. To increase the performance of MIMO configurations, there is also a calibration ADC available to calibrate the LO path before it is exported.  The LO signal then enters a filter bank with the same lowpass and bandpass filters used in both the NI PXIe-5644R RF receiver and transmitter, as shown in Figure 8.

Figure 8: NI PXIe-5644R Synthesizer LO High-Level Block Diagram

Spectral Purity

When the incoming RF signal mixes with the LO, it inherits the spectral skirt of the LO. For this reason, it is very important for the LO to have good spectral purity. Frequency-banded VSAs typically use off-the-shelf integrated synthesizers, which are typically not as good as a traditional discrete synthesizer. The NI PXIe-5644R is designed to be a wideband instrument. As such, it features a traditional discrete synthesizer built from scratch. This allows the NI PXIe-5644R to have excellent measurement performance across the entire frequency range of the instrument.

The NI PXIe-5644R has three different PLL bandwidth options, outlined below. The trade-off of these options is phase noise versus settling time.

1. High bandwidth—Lower frequency settling time (250 us), higher phase noise
2. Medium bandwidth—Moderate settling time (500 us), excellent phase noise comparable to the low bandwidth option, which is optimized for narrow frequency bands (500 MHz or less)
3. Low bandwidth—Optimized phase noise, higher frequency settling time (1 ms)

When measuring RF standards such as 802.11ac and LTE, the medium bandwidth option is typically recommended, but the low bandwidth option can also be used if tuning speed is not important. Fast frequency hopping is an example of when the high bandwidth option would be used. Figure 9 shows the difference in phase noise depending on which of these PLL bandwidth options are selected. Figure 10 below shows the phase noise at different frequencies using the medium bandwidth option only.

Figure 9: Measured Phase Noise at 2.4 GHz Versus Loop Bandwidth

Figure 10: Measured Phase Noise at 1 GHz, 2.4 GHz, and 5.8 GHz With the Medium PLL Bandwidth Option

Calibration

Every NI PXIe-5644R is individually calibrated for accurate frequency and amplitude response at the factory. Each ships with a calibration certificate verifying NIST-traceable accuracy levels. External factory calibration adjusts the frequency reference, internal LO path gain, external LO path gain, RF input gain, and RF output gain. For NI PXIe-5644R to continuously meet specifications, a one-year (or two-year with relaxed specifications) factory calibration is recommended.

Calibration Path

NI PXIe-5644R relies on a fixed path between the RF input and RF output calibration sections of the device. This path is facilitated by the SMA-SMA semirigid cable connecting between the CAL IN and CAL OUT front panel connectors. This cable should never be loosened or removed from the front panel of the device, as it prevents proper self-calibration functionality.

Self-Calibration

In addition, self-calibrations are recommended whenever there is a change in the environment’s temperature by more than five degrees Celsius (5° C). Temperature drift can lead to performance degradation for several NI PXIe-5644R specifications. Perform self-calibration to compensate and optimize the performance for a given ambient temperature. Self-calibration adjusts the following parameters of the NI PXIe-5644R to facilitate temperature correction:

• LO path gain
• RF input gain
• RF output gain
• RF input LO leakage
• RF output LO leakage
• RF input image suppression
• RF output image suppression

The calibration synthesizer provides a stable frequency pared with a low distortion amplifier to provide stable amplitude. The calibration table on the device sweeps both frequency and power. There is also vector calibration over frequency. This advanced calibration technique is one of the reasons the NI PXIe-5644R can achieve the R&D-grade performance in such a small form factor.

Next Steps

Watch the webcast 

See the product details 

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8 Ratings | 4.88 out of 5

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