RIO Mezzanine Card Reference Design with NI Multisim and NI Ultiboard

Publish Date: Feb 06, 2012 | 0 Ratings | 0.00 out of 5 |  PDF

Overview

This reference design provides engineers with the various files and background to define their own RIO Mezzanine Card for the NI sbRIO-9605 and sbRIO-9606. All files and designs are available for National Instruments suite of design tools: NI Multisim capture and simulation, and NI Ultiboard layout and routing.

Table of Contents

  1. Introduction
  2. Design Information
  3. RMC Connector in Multisim
  4. Reference Design Schematic
  5. Reference Design Layout
  6. Reference Design Fabrication Files
  7. Additional Resources

1. Introduction

NI Single-Board RIO products are designed for high-volume and OEM embedded control and data acquisition applications that require high performance and reliability. These devices are powered by NI LabVIEW FPGA and LabVIEW Real-Time technologies so you can customize them with easy-to-use graphical programming tools.  

NI sbRIO-9605 and sbRIO-9606 are digital I/O-only embedded devices featuring a real-time processor, reconfigurable FPGA and a RIO Mezzanine Card (RMC) connector, which is a high-speed, high-bandwidth connector that provides direct access to the processor and 96 3.3 V digital I/O FPGA lines. The RMC connector enables users to design custom daughter cards, or RIO Mezzanine Cards, to further customize NI Single-Board RIO to fit specific applications requiring custom circuitry or combination of I/O and peripherals. 

Figure 1 shows the back view of the sbRIO-9606 device with the RMC connector highlighted in yellow.

Figure 1. Back view of the sbRIO-9606 featuring a RMC connector.

For this reference design we use NI Multisim and NI Ultiboard, the circuit design and prototyping tools from National Instruments, to create a custom RIO Mezzanine Card for the sbRIO-9605/9606. NI Multisim features a powerful environment for schematic capture and simulation and provides a database of 22,000+ components from leading manufacturers. Furthermore, Multisim includes more than 90 predefined connector symbols and footprints to develop custom applications for NI hardware systems.

NI Ultiboard is a flexible environment for PCB layout and routing and provides the tools engineers need for quick prototyping. Ultiboard is fully integrated with Multisim, so you can quickly translate a circuit to PCB prototype. Engineers can also export industry-standard formats such as Gerber and DXF for quick prototyping and fabrication.

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2. Design Information

This particular reference design is for the NI sbRIO-9605/9606 boards, the design files are provided as a template so you can begin completing your RIO Mezzanine Cards with Multisim and Ultiboard.

Click here to download a zip file with all the design files.

The zip file contains:

  • Multisim file: sbRIO-9605_9606 Daughter Card.ms12
  • Ultiboard file: sbRIO-9605_9606 Daughter Card.ewprj
  • Netlist file: sbRIO-9605_9606 Daughter Card.ewnet

You need to have Circuit Design Suite (Multisim and Ultiboard) version 12.0 installed to open these files. Visit ni.com/multisim to download an evaluation version.

The custom board on this reference design contains a triple axis digital accelerometer, a 20x4 character LCD screen, a USB port, and some passive components. LabVIEW Real-Time and LabVIEW FPGA are used to define the operation of the sbRIO system. The application running on the FPGA will acquire acceleration from the accelerometer through Serial Peripheral Interface (SPI) bus. This information will be used to determine the position of the text on the LCD. This means that whenever the board is tilted, the text on the screen will move in the direction of tilt, at a speed proportional to the angle of tilt. Please note that discussing the LabVIEW code is beyond the scope of this reference design.

Sixteen FPGA I/O lines are used to control the digital accelerometer and the LCD screen. Table 1 shows the mapping between these components and the FPGA I/O lines.

Table 1. FPGA I/O lines used on the reference design

Component Pin FPGA I/O Line
Accelerometer INT 80
SCK 81
CS 82
SDI 83
SDO 84
LCD Screen DB7 19
DB6 21
DB5 22
DB3 23
DB2 24
DB1 25
DB4 26
DB0 27
R/W 28
RS 29
E 30

Since the FPGA I/Os are 3.3V, it is recommended that you use 3.3V logic components. Higher voltage components can be used as long as they do not directly communicate with the FPGA I/Os, as this will damage the latter. Voltage level buffers can be used to go from 5V to 3.3V and vice versa.  Buffering methods and device selection will be dependent on design needs, and will not be discussed in this document.

Note

Although this design reference library is intended to be as accurate as possible and has been checked by Application Engineers at National Instruments, it is always recommended to closely check documentation provided with the hardware purchase. It is always suggested that you reference materials associated with NI hardware to verify correct pin assignments and to check correct layout guidelines and pin spacing.

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3. RMC Connector in Multisim

The RMC connector used in the sbRIO-9605/9606 devices is a high-density 240-pin Searay connector. The recommended mating connector is the SEAM-40-03.0-S-06-2-A-K-TR. An engineer could spend up to two days creating and testing the symbol and footprint for this connector and even the smallest mistake could result in errors and prototype iterations. In order to save you days of development Multisim features 90+ connector symbols and footprints to interface your custom circuitry to NI hardware.   

Complete the next steps to explore the NI connectors included in Multisim:

  1. Launch Multisim 12.0 and select Place»Component. The Select a Component window opens.
  2. Select the Master Database and the NI_Components Group. Here you will find a number of connector families available in Multisim for M_Series_DAQ, X_Series_DAQ, SCXI, sbRIO, cRIO, and so on. Each family contains accurate symbols and footprints for mating connectors to interface your custom circuitry to NI hardware.   

Figure 2. NI_Components Group in Multisim

  1. Select the sbRIO family and then the NI-sbRIO-9606 component, this is the recommended mating connector for RIO Mezzanine Card designs.
  2. Click OK, you will notice that the connector has been divided in three sections: DIO, MISC and RES, as shown below:

Figure 3. Multi-section component

  1. Place the three sections of the connector on the schematic.

Figure 4. RMC Connector Symbol

The DIO section provides connections for 96 FPGA I/O channels. When designing a daughter board, National Instruments suggests using pins DIO0 through DIO63 first to maintain future compatibility. DIO64 through DIO95 are not guaranteed to be provided on future products.

The MISC section gives access to the power lines, ground and USB (sbRIO-9606 only). Note that the RMC connector provides power (5 V) on pins 54, 60, 66, and 72, however all these pins are being mapped into the 5V pin, this simplifies the symbol. Similarly, the FPGA_VIO rail (pins 234 and 240) are mapped to the FPGA_VIO pin and all the ground pins are mapped to GND pin.

Finally, the REV section groups all the reserved pins of the RMC connector.

Refer to the NI sbRIO-9605/9606 documentation for more details about pinouts.

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4. Reference Design Schematic

  1. Open the file sbRIO-9605_9606 Daughter Card.ms12. This reference design has been organized into various multi-page schematics: RMC_DIO, RMC_MISC, RMC_RES, and Circuitry. On the left hand side of the Multisim user interface you will find the Design Toolbox, here you can manage various elements in the schematic (circuit files, projects, design blocks).  

Figure 5. Design Tooolbox

The multi-page approach is recommended for designs that can be divided in flat sequential blocks. Moreover, every page of the design is saved within the same file, making it easy to migrate from one computer to another. Multisim also supports Hierarchical Blocks and Subcircuits, which can help you organize and modularize your schematic design.

  1. Click on the RMC_DIO page, here you will find the DIO section of the RMC connector. This section provides connections to 96 FPGA I/O channels. In this reference design we use 16 FPGA I/O lines to control the accelerometer and the character LCD.   

Figure 6. DIO Section of the RMC Connector

In order to simplify wiring, we are using a bus (BUS_DIO) to carry multiple nets. The Bus Vector Connect utility can be used to facilitate the connections between multiple pins and buslines. Refer to Figures 7 and 8.

Figure 7. Bus Vector Connect

Figure 8. Connections created by Bus Vector Connect

Note that we are using a Bus off-page connector to connect this bus to other pages. Hover the mouse over the off-page connector and click on the magnifying glass to display a thumbnail of where the connector is attached.

Figure 9. Buss off-page connector

  1. Select the RMC_MISC page. Ground, USB and power lines are connected to the MISC section of the RMC connector. Nets VDD, VCC, USB_D-, USB_D+ and Ground (net 0) need to be available on the Circuitry page, that is why we are using On-page connectors and Global connectors, as shown below:

Figure 10. MISC Section of the RMC Connector

  1. Click on the RES page. The RES section of the RMC connector was placed here as reference. Remember that all the pins included on this section are reserved and they should be left disconnected.
  2. Click on the Circuitry page. Here you will find the custom circuitry that interfaces from the RMC connector to the daughter card. A four pin type A USB connector was added to permit the connection of any USB device to the sbRIO board (sbRIO-9606 only).  

Figure 11. Custom circuitry

If needed you can add more pages to the main file by selecting Place»Multi-page. You can also remover, rename and reorder pages.

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5. Reference Design Layout

  1. Launch Ultiboard (All Programs»National Instruments»Circuit Design Suite 12.0»Ultiboard 12.0).
  2. Select File»Open and browse the file sbRIO-9605_9606 Daughter Card.ewprj. Ultiboard opens the layout file of the custom board.

Figure 12. Ultiboard layout

For this design we selected a four layer board. Two layers (Copper Top and Copper Bottom) are used for routing and the inner layers (Copper Inner 1 and Copper Inner 2) are used for VCC and GND; powerplanes were placed on these layers.

Refer to the dimensional drawing for the sbRIO-9605 and sbRIO-9606 for more details dimensions of the board outline, mounting holes and placement of the RMC connector.

  1. Select View»3D Preview. Ultiboard will display a 3D view of the template file as shown in Figures 13 and 14. You can use your mouse to rotate the board 360 degrees in all directions.

Figure 13. RMC card top view (3D)

Figure 14. RMC card bottom view (3D)

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6. Reference Design Fabrication Files

Ultiboard allows you to export to a number of standard formats including the Gerber format, which is utilized by most fabrication board houses to define a physical prototype. Complete the next steps to export Gerber RS-274X files:

  1. Select File»Export. The Export window opens.

Figure 15. Export dialog box

As you can see, Ultiboard can export other file formats including: DXF, Parts Centroids, NC Drill, and so on.

  1. Select Gerber RS-274X and click on the Export button. The Gerber Settings window opens.

Figure 16. Gerber File Export

In the Gerber Settings window you can select the various layers to export. It is important that you contact your board house and ask them what files they need to fabricate the board.

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7. Additional Resources

Learn more about NI Single-Board RIO

Custom Circuit Design for NI Hardware

Learn more about NI Multisim

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