1. Software and Hardware Requirements
- Multisim 12.0
- LabVIEW 2011
- LabVIEW 2011 Control Design and Simulation Module
- LabVIEW 2011 FPGA Module
- CompactRIO (optional for hardware implementation)
With system-level simulation, you can implement point-by-point simulation between two separate simulation engines: analog SPICE circuitry and digital logic. This functionality is exclusive to the Multisim and LabVIEW platform through an approach called cosimulation. Cosimulation allows a unique time-step negotiation between two simulation engines to create a closed-loop simulation of the complete system. The result is an evaluation of a design that includes all of the system dynamics between the analog and digital modules. Multisim, which is optimized for accurate analog and mixed-signal circuitry, includes a large set of predefined SPICE models from leading semiconductor manufacturers such as Analog Devices, NXP, ON Semiconductor, and Texas Instruments. The LabVIEW simulation engine is dedicated to the effective design and implementation of control logic through a graphical, dataflow representation. This engine provides high-level simulation optimized for embedded digital code for mechanical systems.
Figure 1. Cosimulation With Multisim and LabVIEW
In this reference design, a complete system simulation of a brushed DC motor H-bridge circuit and the pulse-width modulation (PWM) closed-loop control logic is developed. The DC motor is modeled and simulated in Multisim along with the H-bridge transistors and gate drivers. Feedback sensors and quadrature encoding of the motor speed are used to provide LabVIEW with the feedback signals. In LabVIEW, proportional integral (PI) control logic is performed based on the feedback signals from Multisim, and the PWM control signals are reapplied to the Multisim input terminals to control the H-bridge transistor gates. This circuitry regulates the amount of current flowing into the motor. The logic design is simulated using LabVIEW FPGA IP blocks running at 40 MHz.
This tutorial demonstrates an accurate desktop simulation of a prototype before the hardware implementation.
3. Technical Background Documentation
Learn about these related topics:
- LabVIEW and Multisim cosimulation basics
- H-bridge topology
- PID control fundamentals
- DC motor closed-loop control
- PWM fundamentals
4. Design Procedure
The first step of the design is to develop the analog circuitry in Multisim. The circuit includes new models of power electronics components added in Multisim 12.0:
- New models of power metal-oxide semiconductor, field-effect transistors (MOSFETs) with the option of varying the device parameters
- New model for the DC permanent magnet machine
- New models for the incremental encoder and rad/s to rpm converter
Multisim analog circuits contain three different circuit schematics:
- The first circuit is based on MOSFET models from International Rectifier (IRF953 and IRF371)
- The second circuit contains SPICE models for two added gate drivers (IR2101) to ensure proper bias of the MOSFET switches
- The first circuit is based on generic MOSFET models
Figure 2. Analog Circuit Schematic With MOSFET Models From International Rectifier (IR)
Figure 3. Analog Circuit Schematic With MOSFET Models and a Gate Driver From IR
With Multisim simulation, you can evaluate electronic parts early in the design flow. SPICE models are accurate models provided by semiconductor manufacturers and based on real device performance. By using these models, you can determine what response to expect from a design before prototype fabrication.
The models of the MOSFETs from International Rectifier enable the evaluation of the real performance of the circuit before leaving the desktop simulation stage. The gate drivers added to the second circuit showed that they introduce negligible signal delay of a few nanoseconds.
If the MOSFETs you are using do not have SPICE models provided by the manufacturer, the enhanced Multisim database includes generic models for MOSFETs with parameters that you can customize according to the component data sheet. The third schematic in Figure 4 shows a circuit based on these generic models.
Figure 4. Analog Circuit Schematic With Generic MOSFET Models
The HB/SC connectors are defined as LabVIEW cosimulation input and output terminals. Table 1 is exported from the spreadsheet view of the Multisim design.
|LabVIEW terminal||Positive connection||Negative connection||Mode||Type|
Table 1. LabVIEW Cosimulation Input and Output Terminal Connection Information
Finally, the Multisim design is loaded as a control design and simulation block in LabVIEW. The whole system simulation is run through the LabVIEW graphical interface, where timing resources are negotiated between LabVIEW and Multisim in the background transparently to the user.
The Multisim design is loaded in LabVIEW as a virtual instrument (VI) and connected to different system blocks to build the complete closed-loop feedback system. Refer to the LabVIEW technical resources home to learn more about the basics of LabVIEW graphical programming and system design.
The Figure 5 block diagram demonstrates the signal paths of the design.
Figure 5. System Diagram
5. LabVIEW FPGA IP Cores
The LabVIEW FPGA Module is well-suited for the intuitive depiction of the inherent parallelism that FPGAs provide. In addition, it provides efficient simulation of FPGA low-level hardware code compared to compiling digital logic for an FPGA, which can take some time.
In traditional control logic design, an engineer develops embedded code separate from the analog circuitry (that it eventually needs to interface to). This lack of coordination in the design approach can result in embedded logic that does not properly account for analog circuitry (for example, the power design) and performs below expectations and specifications. This forces algorithm change and recompiles.
Each code iteration can result in time lost in compiling and deploying (you can easily lose four hours in just the recompile). Accurate cosimulation with the analog world (which is possible with Multisim and LabVIEW) can provide an understanding of complete system performance before prototyping/compiling, thereby reducing prototype iterations and saving time and costs.
The digital control design of this project includes four LabVIEW FPGA IP cores as demonstrated below.
The Proportional Integral IP
In this code, the calculations for the proportional integral control output value are performed based on the user-defined input coefficients (Kp and KI).
Figure 6. Proportional Integral Block Diagram and Interface
The Quadrature Encoder IP
In this code block, the decoded signals indicating the motor speed (A, B, and I) are encoded to restore the actual speed value and provide feedback to the PI block on whether the current motor speed is higher or lower than the desired setting point. Learn more about quadrature encoding.
Figure 7. Quadrature Encoder Block Diagram and Interface
The PWM Generator IP
This code block receives timing input from the user as well as feedback input from the PI control block.
Figure 8. PWM Controller Block Diagram and Interface
The H-Bridge Controller IP
This IP block translates the PWM output into four control signals for the MOSFET switches to determine which diagonal elements should be switched on or off. It also receives input from the user about the switching dead time of the MOSFETs.
Figure 9. H-Bridge Controller Block Diagram and Interface
6. Complete System Architecture
All of these blocks are placed in a control and simulation loop with predetermined fixed step size. The system can run at up to 40 MHz (250 ns step), and a GUI is developed to monitor several system signals such as the motor speed and current.
Figure 10. This complete system architecture block diagram includes the different FPGA blocks and the Multisim circuit design.
With the analog power stage model and digital controller design complete, the entire system is analyzed and optimized using cosimulation. In the cosimulation environment, Multisim and LabVIEW concurrently perform a nonlinear time-domain analysis, exchanging data at the end of each time step. In addition, when LabVIEW is configured to use a variable step size solver, Multisim and LabVIEW are able to negotiate future time steps, which results in a tightly integrated and accurate simulation. The result is that both tools can enforce accuracy requirements that ensure valid simulation results, even in the case of coupled differential equation relationships that span between both solvers.
Throughout the system analysis, to gain insight into the brushed DC motor drive system behavior, various signals inside the embedded FPGA control code and the analog plant model are monitored during cosimulation. The ability to probe any signal (for example, currents/voltages inside a MOSFET/motor, or the dead-time behavior of the control code) allows for the validation of system connectivity and a much deeper understanding of system behavior.1
Figure 11. In this 1 s simulation of the system setting the motor speed from stopping to 1200 rpm, the depicted signals are those of the setting speed (red), the sensed speed from Multisim (yellow), and the motor's actual speed over the course of the simulation (white).
Figure 12. The LabVIEW interface of the system simulation shows the sensed signal in Multisim of the motor's current (green) and the FPGA control signal in LabVIEW (blue) over the course of a 1 s simulation setting the motor speed from stopping to 1200 rpm.
You can combine Multisim and LabVIEW simulation capabilities to create a complete desktop simulation of an electromechanical system that features modeling of a brushed DC motor and adjoining power electronic devices, the analog simulation of the H-bridge circuit, and the digital control block simulation. The point-by-point simulation validates system performance at an early design stage to help you determine the most suitable electronic components, PI control settings, H-bridge drive modes, and system monitoring settings.
1. “An Improved Co-Simulation Approach to Rapidly Prototype, Verify, and Implement Dynamic FPGA-based Embedded Control Systems,” Muris Mujagic, Oleg Stepanov, and Brian MacCleery.