Using the Example Sinewave Model with a VxWorks CompactRIO Target

Publish Date: Jun 15, 2010 | 0 Ratings | 0.00 out of 5 |  PDF

Overview

The LabVIEW Simulation Interface Toolkit (SIT) provides interoperability between models created by users of The MathWorks Inc. Simulink® software and LabVIEW-enabled hardware targets. The Simulation Interface Toolkit automatically generates code to interface with Simulink, resulting in a flexible and easy-to-understand user interface.

Table of Contents

  1. Background
  2. Compiling the Model Using The MathWorks Real-Time Workshop Software 
  3. Developing a Custom FPGA VI for the CompactRIO Reconfigurable Chassis
  4. Using the SIT Connection Manager to Generate the Driver and Host VIs
  5. Running the Sinewave Model on a CompactRIO LabVIEW Real-Time Target
  6. Additional Resources

1. Background

Your models created in Simulink can be executed on a variety of LabVIEW Real-Time embedded controllers, including the CompactRIO.  NI CompactRIO programmable automation controllers are a low-cost reconfigurable control and acquisition system designed for applications that require high performance and reliability. NI CompactRIO features a programmable FPGA that can be mapped to model inputs and outputs.  There are three main steps required to run your simulation on a CompactRIO controller:

  1. Compiling your Model Using The MathWorks Real-Time Workshop® software
  2. Developing a Custom FPGA VI for the CompactRIO Reconfigurable Chassis
  3. Using the SIT Connection Manager to Generate the Driver and Host VIs

For other LabVIEW Real-Time targets, generic directions for these controllers can be found in the Simulation Interface Toolkit How-To: Configuring a Simulation on a Real-Time Target help document.

Note:  The following instructions apply to LabVIEW Simulation Interface Toolkit 5.0 and higher.

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2. Compiling the Model Using The MathWorks Real-Time Workshop Software 

In order to use your model for NI CompactRIO, both a DLL and an OUT file will need to be compiled.  The DLL file allows the SIT Connection Manager to map hardware to the CompactRIO I/O from the Windows Host.  If both model files remain in the same directory, LabVIEW Real-Time will automatically deploy the correct files to the CompactRIO.  Refer to the following directions for compiling your model:

  1. Enable VxWorks support.  Refer to KnowledgeBase 4PNDIMQL:  How Do I Enable VxWorks Support for Simulation Interface Toolkit 5.0? for more information.
  2. Create a DLL file for your model.  Refer to Simulation Interface Toolkit Help:  Converting a Model into a Model DLL for more information.  

    Note:  KnowledgeBase 4QRF55GH: Can I Use a Free Compiler with Simulation Interface Toolkit (SIT)? contains steps for using a free compiler to create the DLL file.

  3. Create the OUT file by following similar directions to the previous step, except select nidll_vxworks.tlc as the System target file instead of nidll.tlc in your Model's Configuration Parameters window.

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3. Developing a Custom FPGA VI for the CompactRIO Reconfigurable Chassis

The FPGA VI will be used in the SIT Connection Manager to map the I/O channels to your model.  The instructions in Simulation Interface Toolkit Help:  Creating a Custom FPGA Bitfile walk through this process.

Note:  There is a pre-compiled bitfile for the cRIO-9103 backplane.  It contains I/O for a backplane with the NI 9215, NI 9263, NI 9411, and NI 9474 modules.  In most cases, however, you will probably need to compile a custom FPGA VI.

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4. Using the SIT Connection Manager to Generate the Driver and Host VIs

Once the model OUT file and FPGA VIs have been generated, the SIT Connection Manager can generate the necessary LabVIEW VIs to execute the simulation on the CompactRIO.  The Driver VI interfaces with the model OUT file and controls the hardware I/O.  The Host VI allows us to probe specific signals in the simulation and retrieve data from the I/O.

Refer to Simulation Interface Toolkit Help:  Specifying the Model DLL and Execution Host for directions on navigating the SIT Connection Manager.

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5. Running the Sinewave Model on a CompactRIO LabVIEW Real-Time Target

The following steps use the example sinewave.mdl file that has been compiled into a .OUT file.  The hardware tested is a cRIO-9014 with a cRIO-9101 backplane.  The backplane has an NI 9215 ±10V Analog Input module and an NI 9263 ±10V Analog Output Module.  The result of this setup is a model that sums the input signal with a user configurable sine wave, sending the result to the analog output channel.

  1. In LabVIEW, create a blank VI.  This will be the Host VI.
  2. Add a Graph indicator; this will be used to display the result of the AI input signal and the sine wave.
  3. Add a Slider control named Amplitude; this control will change the amplitude of the sine wave.  The Model Controls in the figure below are automatically added to the Front Panel after the SIT Connection Manager is configured.

Figure 1:  Host VI Front Panel

  1. Open the SIT Connection Manager by going to Tools»SIT Connection Manager…
  2. Select Real-Time Target as the Execution Host.  Browse to the DLL file previously compiled (sinewave.dll).  Select the CompactRIO target that will execute the simulation.

    Note:  We compiled both a DLL and OUT file previously because the manager only recognizes the DLL; the DLL file allows the SIT Connection Manager to map hardware to the CompactRIO I/O from the Windows Host.  If the OUT file is in the same directory as the DLL, LabVIEW Real-Time will automatically download the correct file to the CompactRIO controller.

Figure 2:  Selecting the Model DLL and LabVIEW Real-Time Target

  1. In the Mappings category, map the Waveform Graph to the Sum signal of the model and the Amplitude control to the Sine Wave/Amplitude signal of the model.

Figure 3:  Mapping the Host VI's Controls and Indicators to the Sinewave Model

  1. In the Hardware I/O category, select Configure HW I/O to map the cRIO modules to the model I/O.
  2. Right-click the CompactRIO target in the device tree and select Add Device»NI-FPGA.  If the custom FPGA was built correctly, the dialog box should select your custom bitfile.

Figure 4:  Selecting Your Custom FPGA Bitfile

  1. Map an Analog Input channel to the In1 Model input and an Analog Output channel to the Out1 Model Output.

Figure 5:  Mapping the FPGA I/O to the Model I/O

  1. Close the HW I/O Mapping dialog and press OK in the SIT Connection manager to begin generating the Driver VI and the Host VI.

The generated Host VI can be used to execute the simulation on the CompactRIO controller.  Press the Run button to deploy the model files to the CompactRIO and use the Model Controls on the Front Panel to run the simulation.

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6. Additional Resources

Follow the directions in Simulation Interface Toolkit Help:  Building a Driver VI Startup Application to execute the simulation automatically after powering up the CompactRIO controller.

For additional help and how-tos on using the Simulation Interface Toolkit, refer to the Simulation Interface Toolkit Help online files.

MATLAB®, Simulink®, and Real-Time Workshop® are registered trademarks of The MathWorks, Inc.

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