When designing embedded systems, timing is critical – whether trying to ensure that a control loop executes dependably, that an I/O signal is responded to quickly, or that processing is fast enough to meet application requirements. Building a system that can handle these timing demands starts with hardware; it must provide the right balance between size, power consumption, processing throughput, and latency. In addition, software plays a key role in regulating execution, responding to interrupts, and balancing time between computing tasks.
While integrating embedded hardware and software with timing in consideration can be a time consuming challenge, but NI LabVIEW 2010 software and NI reconfigurable I/O (RIO) hardware reduce the effort needed to build reliable, deterministic systems that can handle even the most demanding applications. Read on to learn about NI RIO hardware featuring real-time CPUs and field-programmable gate arrays (FPGAs), and how timing features built-into LabVIEW 2010 help engineers, scientists, and embedded designers take advantage of this hardware to create robust, responsive applications.
2. NI RIO Hardware Features Real-Time CPUs and High-Performance FPGAs
National Instruments embedded hardware targets are based on the RIO architecture, which includes a CPU commonly running a real-time OS and one or more FPGAs. With this combination, you can accomplish tasks that require nanosecond resolution timing or massive parallelism in FPGA hardware, while the CPU efficiently executes computationally intensive operations such as floating-point math. Communication between the FPGA(s) and CPU typically takes place over a PCI bus, and the included NI-RIO driver provides a straightforward, powerful data transfer interface from either LabVIEW or C.
The end result is a flexible platform that is ideal for a wide variety of embedded prototypes and designs. And, because the NI-RIO architecture is standard between many different hardware targets, including NI Single-Board RIO and NI CompactRIO, you can maximize code reuse when deploying applications to rugged or cost-optimized embedded devices.
Figure 1. NI Reconfigurable I/O (RIO) embedded devices are built around a common architecture featuring real-time CPUs, FPGAs, and modular I/O
For example, Ventura Aerospace used NI Single-Board RIO, along with LabVIEW, to create a fire suppression system capable of preventing catastrophic fires on FedEx freighter aircraft. Deterministic control algorithms, networking, and data logging were handled on the real-time CPU, while other critical tasks were implemented in hardware on the FPGA.
3. LabVIEW 2010 and Built-In Timing Simplify the Programming of Deterministic, Reliable Systems
Not only can you use LabVIEW graphical programming to target CPUs (including those running a real-time OS) and FPGAs (including those in RIO hardware targets), but the LabVIEW language itself has been designed from the ground up with timing and synchronization in mind. Below are just some examples of how LabVIEW, along with the LabVIEW Real-Time and LabVIEW FPGA modules, makes timing straightforward for embedded applications.
4. Integrated Timing Features in the LabVIEW Real-Time Module
Programming Deterministic, Closed-Loop Applications with LabVIEW Real-Time and the Timed Loop
The LabVIEW 2010 Real-Time Module extends LabVIEW graphical programming to both NI real-time hardware targets (including RIO devices) and selected third-party PC hardware. Depending on the hardware target, LabVIEW Real-Time automatically makes use of either standard VxWorks or ETS real-time OS components (included) to ensure deterministic, hard real-time performance.
When programming a closed-loop control application with LabVIEW Real-Time, the Timed Loop provides an intuitive way to periodically execute a subset of code, synchronize the loop rate with hardware, prioritize multiple loops, or even assign a loop to a certain CPU core – all with a few mouse clicks. In addition, you can choose from kilohertz, megahertz, or custom clocks as the basis of your loop timing.
Figure 2. The LabVIEW Timed Loop enables you to intuitively configure loop timing, synchronization with I/O hardware, real-time code priority, CPU affinity, and more.
Synchronizing Timed Loops across Multiple Targets
You can take advantage of IEEE 1588 synchronization on hardware devices programmed with LabVIEW Real-Time to ensure that a given operation happens nearly simultaneously across many embedded systems. Depending on the device you are using, submillisecond software and/or submicrosecond hardware IEEE 1588 synchronization may be supported.
To take advantage of software-based synchronization across hardware targets in LabVIEW Real-Time, use the Timed Loop along with the Absolute Timing source setting. After configuring the Timed Loop, simply wire in a start timestamp and select run to begin loop execution on multiple systems at the same time.
Figure 3. You can use IEEE 1588 time synchronization along with the LabVIEW Timed Loop to simultaneously start an operation on several distributed embedded devices (NI CompactRIO shown above).
Using the NI Real-Time Execution Trace Toolkit for Detailed Timing Analysis
When used with the LabVIEW Real-Time Module, the Real-Time Execution Trace Toolkit can show detailed information about thread and subVI execution time, priorities and inheritance, and more. You can use the toolkit to not only optimize your real-time applications but also help identify potential issues such as priority inversion or race conditions.
Running .m Files Deterministically on Real-Time Hardware
If you have existing .m file code, you can use the NI LabVIEW MathScript RT Module to run that code deterministically on an embedded system that you program with LabVIEW Real-Time. Essentially, this makes the once complex path to hardware for .m files straightforward and quick. Just combine your .m file with LabVIEW graphical code using the MathScript Node, and drag and drop your application onto the real-time target within the LabVIEW project.
5. Timing Features Built into the LabVIEW FPGA Module
Optimizing FPGA Applications with the Single Cycle Timed Loop
The single-cycle Timed Loop in the LabVIEW 2010 FPGA Module removes registers from inside the loop so you can optimally run a piece of compatible code. This makes loop rates as high as 40 MHz possible for critical operations that need to execute reliably in hardware. Furthermore, code inside a single-cycle Timed Loop takes up less space on the FPGA, leaving you with more space for other tasks.
Figure 4. The LabVIEW FPGA single-cycle Timed Loop enables you to run a section of code optimally at loop rates of up to 40 megahertz.
Using the Loop Timer to Regulate FPGA Code Execution
Executing an operation periodically on an FPGA is as easy as using the Loop Timer inside individual loops on your LabVIEW FPGA block diagram. Using the Loop Timer, you have the option to control the timing of a loop as a multiple of the hardware clock with loop periods in the order of nanoseconds, microseconds, or milliseconds. With a default clock rate of 40 MHz, the Loop Timer can be used to achieve loop rates in multiples of 25 ns.
Synchronizing Real-Time and FPGA Application Timing with Interrupts
With selected FPGA hardware targets, you can generate interrupts from FPGA applications to notify real-time host programs of events, such as data being ready, an error occurring, or a task finishing. By taking advantage of the Interrupt function in LabVIEW FPGA and the Wait on Interrupt method in LabVIEW Real-Time, you can synchronize your entire embedded system. Up to 32 interrupts are available.
Identifying Bottlenecks with Critical Path Highlighting
Identifying and correcting timing violations during FPGA application development can be tedious. To ease this process, use the LabVIEW FPGA Module to quickly highlight every operation in the critical path and jump to the appropriate location in the source code, where you can remedy the problem by programming more efficiently or using additional pipeline stages.
Figure 5. Critical Path Highlighting in the LabVIEW FPGA Module enables you to quickly identify bottlenecks in your FPGA application.
6. Consider LabVIEW and NI RIO for Your Next Embedded Prototype or Design
NI RIO hardware and LabVIEW have been used successfully to provide tight timing and reliable operation in thousands of embedded prototypes and deployed systems. When planning your next embedded design, consider the time and cost savings that powerful, flexible, off-the-shelf hardware can provide – as well as the advantages of using LabVIEW graphical programming, built-in timing features, and hundreds of IP libraries to shorten your development cycle.
>> Learn more about the NI Embedded Software Evaluation Kit, which contains fully functional NI Single-Board RIO hardware, LabVIEW Real-Time and LabVIEW FPGA evaluation software, and detailed instructions.