PCI Express Clock Specifications and Effect on NI MXI-Express RIO Interoperability

Publish Date: May 20, 2014 | 0 Ratings | 0.00 out of 5 |  PDF

Overview

National Instruments strives to provide quality products and ensure compatibility and flexibility for users. To achieve this goal, NI participates in industry-standard technology development groups and develops products that adhere to industry standards, where these standards exist, to ensure interoperability with other products. NI products interact effectively with components from other companies that are designed to industry standards. Examples include NI products based on GPIB, VXI, PCI, PCI Express, USB, PXI, and PXI Express.

NI MXI-Express RIO chassis implement a x1 PCI Express link to the host PC through a PCI Express board such as the NI PCIe-8362. The interfaces of PCI Express boards like the NI PCIe-8362 meet PCI Express standards. To ensure interoperability, these standards specify parameters such as voltage levels, signal encoding, bit rate, packet size, error detection mechanisms, and timing. A 100 MHz reference clock, provided by the host computer, is specified with detailed timing characteristics to serve as a timing reference for device communication. Peripheral cards and adapters—including graphics cards, network and storage adapters, communication devices, field-programmable gate arrays (FPGAs), and instrumentation cards that are designed to the specification—can communicate with the host PC if the host also complies with the specification.

Unfortunately, during interoperability testing on the NI MXI-Express RIO chassis, many PCs violated the specifications for the 100 MHz reference clock. This document describes the problem and recommends which PCs to use with an NI MXI-Express RIO expansion chassis.

Table of Contents

  1. Spread-Spectrum Clocking
  2. Clocking for NI MXI-Express RIO Chassis 
  3. Recommendations for Maximum Interoperability
  4. References
  5. Additional Resources

1. Spread-Spectrum Clocking

Developers of the PCI Express specification realized that a constant-frequency 100 MHz clock may present a problem with radiated emissions standards. These emissions standards were developed to minimize the chance of devices interfering with each other. For example, a PC with a constant 100 MHz clock may generate emissions that interfere with your FM radio or instrumentation. To aid systems in complying with these emissions regulations, the PXI Express system reference clocks are frequency-modulated. Modulation reduces the peak energy in clocking signals and spreads it across several adjacent frequencies, reducing the chance of interfering with other devices. Clocks with this type of frequency modulation are known as spread-spectrum clocks. 

This reference clock frequency modulation impacts system timing; however, PC technology specifications are designed with these timing impacts in mind. The modulation behavior is defined by various parameters so that designers know which operational characteristics are required by tier components. The modulation is specified by Chapter 4 of the PCI Express specification, which stipulates a modulation rate of 30 to 33 kHz and modulation amplitude of 0 to –0.5 percent. This means that you can downspread the clock, and data based on the clock frequency, by 0.5 percent from the nominal clock frequency (100 MHz) and change it at a rate not to exceed 33 kHz.

The figure below shows the modulated clock frequency of the PCI Express clocks of several systems over approximately 90 μs. The vertical scale is the frequency of an individual clock period and the horizontal scale is the time in seconds. The 90 μs capture on this plot illustrates almost three full cycles of the clock modulation. All of the clocks comply with the maximum 33 kHz modulation rate.

The blue trace shown in the figure below depicts a PCI Express reference clock that is properly modulated: the frequency of the modulation is between 30 and 33 kHz, the amplitude of the modulation is 0.5 percent of 100 MHz (500 kHz), and it is downspread (the maximum frequency is 100 MHz). If PCs violate this clock specification, then add-in cards designed to work with the specification cannot guarantee complete functionality. 

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2. Clocking for NI MXI-Express RIO Chassis 

NI MXI-Express RIO chassis implement a x1 PCI Express link to the host PC through a PCI Express board like the NI PCIe-8362. The interfaces of PCI Express boards such as the NI PCIe-8362 are governed by both the PCI Express 1.1 and 2.0 specifications.

During the development of the NI MXI-Express RIO chassis, NI discovered that several systems used to test performance and interoperability do not follow the reference clock specifications as set forth in Section 4.3 of the PCI Express specification. These clocks failed in different ways. The figure below shows the measured clock data from four different systems. Some were centerspread (modulated +0.25 percent and –0.25 percent) instead of downspread, as shown by the red trace in the figure. This creates an overclocked condition because half the time the clock is faster than the specification allows. Other systems modulated their clocks by almost 1 percent instead of 0.5 percent, or twice the amplitude allowed by the specification (as shown by the brown trace in the figure). Another example of a specification violation is the green trace in the figure, which shows a constant-frequency 100.1 MHz clock, violating the 100 MHz maximum frequency limit.

 

Figure 1. Clock Frequency Over Time

The figure of the clock frequency over time depicts the following:

  • Blue trace: Ideal PCI Express spread-spectrum clock. The modulation frequency is between 30 and 33 kHz, the modulation amplitude is 0.5 percent, and it is downspread (frequency is never more than 100 MHz).
  • Red trace: 0.5 percent centerspread PCI Express clock. This clock violates the PCI Express specification because it is centerspread instead of downspread. The amplitude of the modulation is 0.5 percent, but because it is centerspread, the clock frequency peaks as high as 100.2 MHz, violating the 100 MHz maximum frequency limit.
  • Brown trace: 1 percent centerspread PCI Express clock. This clock violates the PCI Express specification in two ways:
    – It is spread almost 1 percent instead of 0.5 percent.
    – It is centerspread instead of downspread. This means the frequency of this clock peaks almost as high as 100.5 MHz.
  • Green trace: Constant-frequency 100.1 MHz PCI Express clock. This clock violates the PCI Express specification because its frequency is more than the maximum limit of 100 MHz. The PCI Express specification allows clocks to have a constant-frequency (nonspread-spectrum), but the frequency must be 100 MHz.
  • Pink markers: 300 ppm tolerance around 100 MHz allowed by the PCI Express specification. Clock frequency must not exceed the top pink marker. 
  • Orange marker: 0.5 percent downspread from 100 MHz (100 MHz–0.5% = 99.5 MHz). Clock frequency must not dip below the orange marker.

    An NI MXI-Express RIO chassis expects the host PC to feature a compliant clock for proper operation. The systems providing the green, brown, and red data sets violate the clocking parameters and, therefore, an NI MXI-Express RIO chassis may not operate properly.

    Note: If LINK LED on your MXI-Express RIO is blinking yellow, this indicates the PCI Express clock provided is incompatible with MXI-Express RIO.

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3. Recommendations for Maximum Interoperability

A survey of commercially available desktop computers conducted by National Instruments at the time of this writing found that up to a third of these systems had clocks that did not comply with the PCI Express specification.

Two of the noncompliant systems had the ability in the BIOS to disable spread-spectrum modulation, and, when this was completed, the clock became compliant with the specification. The second observation is that several vendors provide a product portfolio that contains both compliant and noncompliant systems. Therefore, a vendor cannot be said to always break the specification and cause compatibility problems. This creates confusion in the marketplace for users and difficulty for add-in card suppliers.

Large IT suppliers, such as Dell and Hewlett Packard, strive for the greatest compatibility by strictly designing their systems to meet specification requirements. Similarly, NI embedded controllers and rack-mount controllers are designed to fully adhere to specifications requirements. To ensure compatibility with the NI MXI-Express solution, or any other PCI Express peripheral, NI recommends buying systems from these vendors.

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4. References

  1. PCI Express Base Specification 1.1, PCI Special Interest Group, www.pcisig.org
  2. PCI Express Electro-Mechanical Specification 1.1, PCI Special Interest Group, www.pcisig.org
  3. Using CDC590A/2510A PLL With Spread Spectrum Clocking (SSC) Application Note, Texas Instruments, http://focus.ti.com/lit/an/scaa039/scaa039.pdf
  4. Spread Spectrum Technologies, Cypress Semiconductor, Sp www.cypress.com/?id=1215

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5. Additional Resources

Learn more about MXI-Express RIO

Getting Started with the NI MXI-Express RIO Expansion Chassis

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