It is important to think about timing and synchronization requirements when designing a system. The timing system may need to coordinate tasks between instruments, or instruments may need to communicate directly with each other in a way that requires hardware synchronization. Examples of common timing and synchronization tasks include handshaking between a DMM and switch, phase-lock-looping a waveform generator with a digitizer, or synchronizing an RF downconverter with an IF digitizer.
2. Single-Device Synchronization
The simplest synchronized system that one could possibly have is a one device system. This simple system is comprised of several channels that are synchronized to a common on-board clock. These systems require almost no synchronization, as they reside on the same board and all channels have access to clock signals and triggers. Figure 1 shows an example of single-device synchronization.
Figure 1 - Single-Device Synchronization
3. Multi-Device, Single-Chassis Synchronization
When more channels are needed than can be contained on one device, or if more than one type of device is required, then synchronization must be added to our system. Clock signals and triggers must be conveyed to devices in the system in order to synchronize the devices to a common clock and ensure that they start at a known time. The PXI Platform gives the system designer tools such as a backplane clock and matched-length trigger lines that make synchronizing these clock and trigger signals simple. Figure 2 shows the PXI backplane clock and trigger lines.
Figure 2 - Multi-Device, Single-Chassis Synchronization
4. Physically Connected, Multi-Chassis Synchronization
If all the slots in a chassis are filled with modules, and more space is needed, then an additional chassis or multiple chassis are added to the system handle this extra need. Factors such as distance between chassis and required precision of synchronization must be accounted for at this point in the design phase. If the distance between chassis is less than around 200 meters, then the clocks and triggers from the master chassis can be physically connected to the slave chassis with cabling. The longer distances that the timing signals have to travel start to inflict timing errors such as clock skew and clock drift.
For more information on timing errors, please read Synchronization Basics.
Figure 3 shows an example of a multi-chassis system. Notice the clocks and trigger lines connected from the master chassis to the slave chassis.
Figure 3 - Multi-Chassis Synchronization
With PXI-based products, synchronization is commonly conducted by synchronizing each board’s clock to the PXI Chassis 10 MHz clock, which is built in to the backplane of the chassis and accessible through PXI Trigger lines. But what if the devices need a clock of a different frequency?
Phase-Locked Loop (PLL)
A phase-locked loop (PLL) is a feedback circuit designed to allow one circuit board to synchronize the phase of its on board clock with an external timing signal. PLL circuits operate by comparing the phase of an external signal to the phase of a clock signal produced by a voltage controlled crystal oscillator (VCXO). The circuit then adjusts the phase of the oscillator’s clock signal to match the phase of the reference signal. Thus, the original reference signal, and the new signal are precisely in phase with each other.
Phase-lock looping is an extremely powerful synchronization technique when performing data acquisition because it allows multiple boards to lock to a shared reference signal. As a result, these boards can synchronize the phase of their internal 80 MHz or 20 MHz timebase and thus, their sample clocks. Because the phase of each sample clock is synchronized, each board can take a measurement at precisely the same instant. Figure 4 shows a PLL diagram.
Figure 4 - PLL Diagram
5. Time-Referenced, Multi-Chassis Synchronization
If the required distance between chassis is too great for cables to transmit the clock and trigger signals reliably, then time referencing must be used. Protocols such as IEEE 1588, GPS and IRIG-B are used to convey synchronization over large distances. Each has its own pros and cons and the designer must pick which time reference protocol fits their application the best.
For a description of each protocol, please read Synchronization Systems.
Synchronization and Memory Core (SMC)
Today's systems require tightly integrated digital and analog acquisition and generation hardware with tight timing characteristics. Analog and digital instrumentation can no longer be stand-alone systems with disparate timing engines and mismatched analog performance. National Instruments designed the Synchronization and Memory Core (SMC) as the common architecture for a suite of high-speed modular instruments that answer the challenge of testing converged devices.
Precise Timing & Synchronization Engine
Synchronization is key for either synchronizing instruments of the same type (homogeneous synchronization) for channel expansion, or for tightly correlating the input and/or output of two different instruments (heterogeneous synchronization). By definition, mixed-signal test systems require the use of at least two of the three instruments (digitizer, arbitrary waveform generator, and digital waveform generator/analyzer), as shown in Figure 5. Additional applications requiring synchronization are baseband I/Q signal generation and acquisition for communications, RGB video signal generation and acquisition for consumer electronics, digital waveform generation and acquisition of 24 channels for 24-bit ADC and DAC test, and many more.
Figure 5 - Typical Instrumentation Setup for Mixed-Signal Test Synchronization
The goal of synchronization is to be able to generate and receive waveforms precisely among multiple SMC instruments. In the case of two arbitrary waveform generators, for example, this goal demands that two AWGs generate identical waveforms in perfect alignment with the ability to skew the phase between the waveforms. With sampling rates of 100 MHz on all three devices, proper care and attention was given to the clock and trigger distribution between all devices. Sample clock skew adjustment with tens of picoseconds resolution, trigger propagation delay and skew calibration, and picosecond level rms clock jitter on all devices deliver the performance required to integrate all three devices at 100 MS/s at the sub nanosecond level.
Synchronization is implemented by sharing triggers and reference clock between multiple devices. The reference clock can be supplied by the designated master device or by a dedicated high-precision clock source. Each SMC instrument has voltage-controlled crystal oscillators (VCXOs) phase-locked to the PXI 10 MHz reference clock, as shown in Figure 6. To achieve further timing accuracy, you can consider equipment such as rubidium or oven-controlled crystal oscillator (OCXO) based frequency sources. The accuracy of these devices can be better than ±100 parts per billion (ppb). For example, an OCXO source with ±100 ppb accuracy yields a 10 MHz clock with ±1 Hz uncertainty. The NI PXI-6653 Slot 2 timing and synchronization controller is ideal for such applications. It can drive its OCXO clock onto the PXI 10 MHz reference clock lines instead of the PXI backplane clock. Thus, all instruments with VCXOs locked to the 10 MHz OCXO inherit the ±100 ppb accuracy.
Figure 6 - Illustration of High-Speed Sampling Clocks Synchronized Using PLL
Another synchronization technology is TClk. TClk provides a high level of synchronization between instruments by aligning sample clocks that may not be initially aligned despite being phase-lock looped. In addition to SMC, TClk can align sample clocks and keep them aligned over time. Figure 7 below shows a timing diagram of two synchronized devices with and without TClk. Without TClk, the master device started at A, and the slave starts at B. With TClk, both the master and the slave start together at A.
Figure 7 - TCLK Synchronization
With TClk, the SMC generates a local copy of the TClk signal by dividing down the sample clock to a frequency low enough to reliably send and receive triggers. If the sample clocks on a different modules are at different frequencies, TClk is the greatest common factor of those frequencies. The master device pulses a trigger line synchronous to the TClk falling edge to generate a start trigger. All receiving devices, including the master device itself, receive the trigger and start on the next rising edge of TClk. This ensures that multiple devices can react to the same trigger signal in the same sample clock period.
6. Hybrid Synchronization Systems
Most data acquisition systems today are hybrid systems. Hybrid systems combine test and measurement components from modular instrumentation platforms such as PXI and VXI and stand-alone instruments that connect externally across GPIB, USB, and Ethernet/LAN. Figure 8 shows one possible hybrid test system topology.
Figure 8 - Hybrid Test System Topology
One advantage of choosing the PXI platform as the core of a hybrid system is the integrated timing and triggering capabilities that PXI offers. Unlike stand-alone instruments, the moment you plug in PXI modular instruments to the PXI chassis, all timing and triggering lines are instantly connected and ready for use, including access to a highly stable 10 or 100 MHz system clock, and trigger lines offering nanosecond skew. Plus, PXI systems offer advanced options like IRIG A, IRIG B, and GPS. Largely for these benefits, users choose PXI modular instruments for parts of the hybrid system that require the tightest synchronization and connect to stand-alone instruments as peripherals for specialized needs or equipment reuse.