Implementing a Direct Stream Digital Decoder on National Instruments FPGA Platforms

Publish Date: Aug 23, 2013 | 3 Ratings | 4.33 out of 5 | Print | Submit your review

Overview

This document demonstrates how you can use the LabVIEW Digital Filter Design Toolkit to implement a DSD decoder on NI FPGA Platforms.

Table of Contents

  1. Introduction
  2. Designing a Multistage Multirate Filter
  3. Converting the Floating-Point Filter to a Fixed-Point Filter
  4. Validating the Numeric Accuracy of the Fixed-Point Filter on a PC
  5. Generating LabVIEW FPGA Code
  6. Implementing a DSD Decoder on an FPGA Target
  7. Conclusion

1. Introduction

Super Audio CD® (SACD) is a high-resolution CD audio format developed by Sony and Philips. SACD uses Direct Stream Digital® (DSD) technology to oversample audio signals and store them as delta-sigma modulated digital audio. The sampling rate of DSD is 2.82 MHz, which is 64 times the CD audio sampling rate of 44.1 kHz. Because of the high sampling rate, DSD signals can represent analog signals more accurately than a regular CD can.

To retrieve audio signals, a DSD decoder must perform low-pass filtering followed by a 1/64 decimation of the DSD stream. You can use the LabVIEW Digital Filter Design Toolkit to implement a DSD decoder on NI FPGA platforms, such as an NI CompactRIO controller. The DSD decoder acquires DSD signals from a digital input (DI) port, decimates the signals, and returns audio signals to a host computer or an analog output (AO) module. The following figure shows this process.

Because DSD decoding deals with different sampling rates, you must design a multirate filter for a DSD decoder. Normally, you could use either the Multirate FIR Design Express VI or the Multistage Multirate Filter Design Express VI to interactively design a multirate filter. However, because the decimation factor for a DSD decoder is 64, which is very large, a single-stage multirate FIR filter requires a large number of taps to meet the requirement of the frequency response. In this situation, the filter might not process data at the input data rate of 2.82 MHz that DSD requires. Refer to the following inequality for the relationship between the input data rate a decimation filter can handle and the number of FIR taps the filter requires.

If you design a DSD decoder as a single-stage multirate filter, the tap count becomes so large that the previous inequality cannot be satisfied. Therefore, you must design a multistage multirate filter for a DSD decoder. In this situation, you can use only the Multistage Multirate Filter Design Express VI to interactively design the filter.

To complete the tasks in the following sections, you must install the LabVIEW FPGA Module and Digital Filter Design Toolkit. To help you perform these tasks, you can download the dsd_decoder.zip file, which is attached to this document. The dsd_decoder.zip file consists of an example LabVIEW project and some example VIs that you can use as a reference.

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2. Designing a Multistage Multirate Filter

In LabVIEW, place the Multistage Multirate Filter Design Express VI on the block diagram. The following figure shows a configuration of the Multistage Multirate Filter Design Express VI that you can use as a reference.

You can leave this configuration dialog box open after specifying the required parameters on the Floating-Point Design page.

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3. Converting the Floating-Point Filter to a Fixed-Point Filter

To implement a filter on FPGA targets, you must convert the filter from floating-point representation to fixed-point representation. Complete the following steps to convert the floating-point filter you created in the previous section to a fixed-point filter.

  1. Quantize the filter coefficients with different word lengths until the frequency response meets the requirements of DSD. You can quantize the filter coefficients by specifying the Coefficients word lengths, Coefficients scale type, and Gain word length on the Fixed-Point Quantization page. The following figure shows where and how you can specify these values.

Click OK to close the configuration dialog box.

  1. Complete the following steps to use the DFD FXP NStage Mrate Modeling VI to specify other required parameters for the filter.
    1. Place the DFD FXP NStage Mrate Modeling VI on the block diagram.
    2. Right-click the input word length input and select Create»Control.
    3. Repeat step b for the output word length and interstage word lengths inputs.
    4. Specify the input word length, output word length, and interstage word lengths.
    5. Wire the multirate filters out output of the Multistage Multirate Filter Design Express VI to the multirate filters in input of the DFD FXP NStage Mrate Modeling VI. The block diagram now resembles the following figure.

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4. Validating the Numeric Accuracy of the Fixed-Point Filter on a PC

Before you generate LabVIEW FPGA code for the filter you created, you might want to validate the numeric accuracy of the filter. You can validate the filter by using the DFD FXP NStage MRate Simulation VI to simulate the filter on a PC. Complete the following steps to validate the numeric accuracy of the filter you created in the previous section.

  1. Place the DFD FXP NStage MRate Simulation VI on the block diagram.
  2. Wire the multirate filters out output of the DFD FXP NStage Mrate Modeling VI to the multirate filters input of the DFD FXP NStage MRate Simulation VI.
  3. Wire a DSD signal to the signal in input of this VI.
  4. Run the VI.

You can compare the numeric accuracy of the filter you simulate with that of a reference floating-point filter.

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5. Generating LabVIEW FPGA Code

If the numeric accuracy of the fixed-point filter you simulated in the previous section meets the requirements of DSD, you can use the DFD FXP NStage MRate Code Generator VI to generate LabVIEW FPGA code for the filter you created in the Converting the Floating-Point Filter to a Fixed-Point Filter section. Complete the following steps to generate LabVIEW FPGA code for this filter.

  1. Place the DFD FXP NStage MRate Code Generator VI on the block diagram.
  2. Specify the values of the # channels, destination folder, and filter name controls.
  3. Wire the multirate filters out output of the DFD FXP NStage Mrate Modeling VI to the multirate filters input of the DFD FXP NStage MRate Code Generator VI. The block diagram now resembles the following figure.

  1. Run the VI. The VI generates an FPGA filter within a LabVIEW project in the destination folder.

You can find the maximum acceptable sampling frequency per channel for the FPGA filter by multiplying the value of the sampling frequency/FPGA clock indicator of the DFD FXP NStage MRate Code Generator VI by the FPGA clock rate the filter runs at. You can read the FPGA clock rate the filter runs at by right-clicking the FPGA target in the Project Explorer window and selecting Properties»Top-Level Clock. If the maximum acceptable sampling frequency per channel for the FPGA filter does not reach 2.82 MHz that DSD requires, return to the Designing a Multistage Multirate Filter section to increase the number of filtering stages.

If you follow the previous sections and set the value of the # channels control to 1, the generated filter can process signals at an input data rate of 5 MHz, which meets the requirements of DSD on FPGA targets. Therefore, you can implement this filter on an FPGA target.

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6. Implementing a DSD Decoder on an FPGA Target

Drag and drop the filter block of the LabVIEW project you generated in the previous section on the FPGA block of a LabVIEW project that you want to implement the filter on. The following figure shows where to drop the filter block.

Notice that the filter block in the LabVIEW project contains two FIFOs. The input FIFO is DSD_DataIn, and the output FIFO is DSD_DataOut. Notice that the filter block also contains three filtering VIs that represent each of the three stages you designed in the Designing a Multistage Multirate Filter section.

Right-click the FPGA target in the LabVIEW project and select New»VI to create a DSD decoder VI. Drag and drop the two FIFOs and three filtering VIs on the block diagram of the DSD decoder VI. You must specify other parameters as your project requires. The following figure shows the block diagram of a DSD decoder VI that you can use as a reference.

In the previous figure, the input FIFO, which receives DSD signals from a DIO node, is in the Timed Loop on the top. The filtering VIs, which filter and decimate DSD signals, is in the middle. The output FIFO, which sends audio signals to a DMA upload FIFO, is in the Timed Loop at the bottom. You now can run this DSD decoder VI on the FPGA target.

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7. Conclusion

This document demonstrates how you can use the Digital Filter Design Toolkit to implement a DSD decoder on NI FPGA Platforms. The seamless connection between LabVIEW, the Digital Filter Design Toolkit, and NI FPGA Platforms makes them an integrated development platform, which saves time and cost when you design and verify a filter.

 

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