Implementing a Fixed-Point Octave Filter on an FPGA Target

Publish Date: Nov 30, 2018 | 0 Ratings | 0.00 out of 5 | Print | Submit your review

Overview

This document demonstrates how you can use the LabVIEW Digital Filter Design Toolkit to implement a fixed-point octave filter on an FPGA target.

Table of Contents

  1. Introduction
  2. Designing a Fixed-Point Octave Filter on an FPGA Target
  3. Generating LabVIEW FPGA Code for a Reference Fixed-Point Filter
  4. Modifying the Generated Code
  5. Simulation Results
  6. Summary

1. Introduction

Octave analysis is one of the most useful methods for analyzing sound and vibration systems. National Instruments provides the CompactRIO platform and LabVIEW FPGA technology that you can use to perform octave analysis. This document demonstrates how you can use the LabVIEW Digital Filter Design Toolkit to implement a fixed-point octave filter on an FPGA target.

The IEC 1260:1995 and ANSI S1.11-2004 international standards define the central frequency and boundary frequencies for the one-octave frequency band, third-octave frequency band, and other octave frequency bands. For example, these standards define the third-octave frequency band with the following equations:

where    represents the central frequency for the third-octave frequency band

 represents the lower boundary frequency for the third-octave frequency band

 represents the higher boundary frequency for the third-octave frequency band

n is the index for the third-octave frequency band

You can use the Digital Filter Design Toolkit to design and generate LabVIEW FPGA code for fixed filters, but if you modify the coefficients of a filter implemented on an FPGA target, the fixed-point model of the filter also changes. You then must regenerate the FPGA filter. However, for octave analysis, you often must select different frequency bands. If you use a fixed filter, you must recompile the code each time you select a different frequency band.

One solution to this problem is using different filters for different frequency bands. The following figure shows this solution.

However, this solution requires more FPGA resources than using a single filter. Instead of using different filters for different frequency bands, you can use the Digital Filter Design Toolkit to design a filter that is reconfigurable at run time. The following figure shows this solution.

This document demonstrates how you can use the Digital Filter Design Toolkit to design a filter that is reconfigurable at run time. To complete the tasks in the following sections, you must install the Digital Filter Design Toolkit, NI Sound and Vibration Measurement Suite, and LabVIEW FPGA Module. You also must download the octave_filter_on_fpga.zip file, which is attached to this document. The octave_filter_on_fpga.zip file consists of VIs necessary for the tasks, an example LabVIEW project, and some example VIs.

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2. Designing a Fixed-Point Octave Filter on an FPGA Target

The Sound and Vibration Measurement Suite provides VIs you can use to design floating-point octave filters that comply with the IEC 1260:1995 and ANSI S1.11-2004 standards. You can use these floating-point octave filters on an FPGA target by converting these filters to fixed-point representation.

To convert a floating-point filter to a fixed-point filter, you must quantize not only the filter coefficients but also the following data and operations in the filtering process:

  • Inputs
  • Outputs
  • Multiplicands
  • Products
  • Sums
  • Delays

The Digital Filter Design Toolkit provides quantization settings applicable for all frequency bands of filters.

Exploring Possible Options for Octave Filters

Complete the following steps to explore possible options for octave filters.

  1. Open the Easy Analyze Octave VI. This VI is contained in the .zip file attached to this document.
  2. Set the coefficients a/k word length and run the VI. The VI returns integer word lengths for each octave filter. A larger integer word length means the filter coefficients have a larger dynamic range and require more bits for precision.
  3. Examine the integer word length the VI returns for all frequency bands of filters. Notice that the integer word lengths are similar for all frequency bands of filters. Therefore, you can set one quantization method for all octave filters.

Ensuring Uniformity among Quantizer Settings for Different Frequency Bands

Complete the following steps to ensure uniformity among quantizer settings for different frequency bands.

  1. Open the Advanced Analyze Octave VI. This VI is contained in the .zip file attached to this document.
  2. Use the information you acquired in the Exploring Possible Options for Octave Filters step to configure the quantization settings. You can use the DFD FXP Quantize Coef subVI to set the integer word length for coefficients. You must set the integer word lengths for coefficients to the maximum value of coefA you acquired in the Exploring Possible Options for Octave Filters step. Make sure you use only one quantization setting for all octave filters.

Comparing the Frequency Responses of the Fixed-Point Filters with Those of the Reference Floating-Point Filters

Run the Advanced Analyze Octave VI to compare the frequency responses of the fixed-point filters with those of the reference floating-point filters. Make sure there are no significant differences between the frequency responses of the fixed-point filters and those of the floating-point filters. The following figure shows this comparison.

You then can use the current scaling and quantization settings to complete the following step.

Generating Coefficients for All Frequency Bands of Octave Filters

Complete the following steps to generate coefficients for all frequency bands of octave filters.

  1. Open the Octave FPGA Filter VI. This VI is contained in the .zip file attached to this document.
  2. Configure the scaling and quantization settings as you did in the Comparing the Frequency Responses of the Fixed-Point Filters with Those of the Reference Floating-Point Filters step. The following figure shows the block diagram of the Octave FPGA Filter VI.

  1. Run the VI.

The Get Octave Integer Coef subVI returns the a_IIRIIT, b_IIRIIT, and gain coefficients that you will later use. This subVI is contained in the .zip file attached to this document.

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3. Generating LabVIEW FPGA Code for a Reference Fixed-Point Filter

Use the Code Generate Octave VI to generate a LabVIEW project that contains all the files you need to implement a fixed octave filter on an FPGA target. This VI is contained in the .zip file attached to this document. Specify the destination folder and, optionally, the number of channels the VI processes in the # channels control.

Run the VI. The DFD FXP Code Generator subVI returns the maximum sampling rate the generated filter can process. Refer to the DFD FXP Code Generator topic of the LabVIEW Help, available by selecting Help»Search the LabVIEW Help in LabVIEW, for more information about this subVI.

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4. Modifying the Generated Code

In this section, National Instruments uses the one-octave frequency band as an example to show how you can modify the generated code to design a filter that is reconfigurable at run time. The octave_modified folder contains a generated project and some modified VIs that you can use as a reference. This folder is contained in the .zip file attached to this document.

Open the project you generated and find the Octave Filter VI by selecting Project»My Computer»DFDT Filter Target»Octave Block. You can compile the Octave Filter VI and test it on an FPGA target. However, the generated code represents a fixed filter. To design a filter that is reconfigurable at run time, you must modify this code. Complete the following steps to modify the generated code.

  1. Open the Octave Filter VI.
  2. Find the b_IIRIIT and a_IIRIIT block diagram constants. These constants store the filter coefficients.
  3. Right-click each constant and select Change to Control.
  4. Add three connectors for the b_IIRIIT, a_IIRIIT, and gain controls to the front panel. After you make these changes, the filter becomes reconfigurable. The following figure shows steps 3–4.

  1. Enter the values of b_IIRIIT, a_IIRIIT, and gain. You acquired these values in the Comparing the Frequency Responses of the Fixed-Point Filters with Those of the Reference Floating-Point Filters step of the Designing a Fixed-Point Octave Filter on an FPGA Target section. You can select different octave frequency bands by changing the control values.

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5. Simulation Results

National Instruments has validated the performance of the generated fixed-point octave filter by performing the following tests:

  • Feeding a series of sine waves into the octave filter—The fixed-point filter coincides with the reference floating-point filter in frequency response. The following figure shows this test result.
  • Feeding wide-band noise into the octave filter—The fixed-point filter coincides with the reference floating-point filter in frequency response. The following figure shows this test result.
  • Examining the time domain waveform of noise input—The difference between the fixed-point filter and the reference floating-point filter is within the RMS value of 10-7. The following figure shows this test result.

The previous test results show that the performance of the fixed-point octave filter matches that of the reference floating-point octave filter.

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6. Summary

This document demonstrates how you can use the Digital Filter Design Toolkit to implement a fixed-point octave filter on an FPGA target. You first use the Digital Filter Design Toolkit to analyze the fixed-point behavior of a group of octave filters. If you find common properties among the filters, you can modify the octave filter that the Digital Filter Design Toolkit generates and design a filter that is reconfigurable at run time.

IP Corner addresses issues and presents technical information on LabVIEW FPGA application reusable functionality, also known as FPGA IP. This article series is designed for those interested in learning, testing, or discussing topics to make FPGA designs better and faster through the reuse of IP.

 

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