1. Introduction
Figure 1. Multiply Function in LabVIEW
Multiplication is something that you probably take for granted in fieldprogrammable gate array (FPGA) applications. How difficult could it be to multiply two numbers together? Computers do it all the time, right? The fundamental architecture of a processorbased system (see Figure 2) includes a dedicated calculation engine called the arithmetic logic unit (ALU). The ALU is responsible for all math operations in everything from fourfunction calculators to Pentium 4 processors.
Figure 2. Von Neumann Processor Architecture
FPGAs, however, have no ALU, and all operations involve configurable logic blocks that are wired up to define a custom hardware circuit (see Figure 3).
Figure 3. An FPGA Composed of Unwired Logic Blocks to Implement a Custom Circuit
You can use logic resources such as flipflops and lookup tables (LUTs) to perform any type of functionality, but complex math operations like multiplication are extremely resourceintensive. For a frame of reference, refer to Figure 4, a schematic drawing of one way to implement a 4bit by 4bit multiplier using combinatorial logic.
Figure 4. Schematic Drawing of a 4Bit by 4Bit Multiplier
Now imagine multiplying two 32bit numbers together, and you end up with more than 2,000 operations for a single multiply. Because of this, many FPGAs have hardwired multiplier circuitry to save on LUT and flipflop usage in math and signal processing applications. When using a multiply function in the LabVIEW FPGA Module, the compiler tries to use all prebuilt multipliers before building additional ones out of logic resources. Table 1 shows the number of multipliers across various FPGA families.

VirtexII 1000 
VirtexII 3000 
Spartan3 1000 
Spartan3 2000 
Virtex5 LX30 
Virtex5 LX50 
Virtex5 LX85 
Number of Multipliers 
40 
96 
24 
40 
32 
48 
48 
Type 
18x18 
18x18 
18x18 
18x18 
DSP48E Slices 
DSP48E Slices 
DSP48E Slices 
Table 1. Multiplier Resources for Various FPGAs
VirtexII and Spartan3 FPGAs have 18bit by 18bit multipliers, whereas the new Virtex5 family of FPGAs has DSP48E slices with 25bit by 18bit multipliers.
2. Using Multipliers in LabVIEW FPGA
Consider a 16bit example in LabVIEW FPGA using an 18bit by 18bit multipliers. The block diagram shown in Figure 5 multiplies two 16bit numbers together of integer 16 (I16) data type. In LabVIEW, the default output data type when multiplying two I16 numbers is also I16.
Figure 5. Multiplying Two 16Bit Numbers in LabVIEW FPGA
An 18bit by 18bit multiplier has two fixed 18bit inputs and a fixed 36bit output to represent all the possible values that can result from multiplying two 18bit numbers. When multiplying two 16bit numbers using one of these multipliers, the corresponding circuit that gets synthesized is shown in Figure 6.
Figure 6. 18x18 Multiplier Used to Calculate the Product of Two 16Bit Numbers
The two 16bit registers are wired to the inputs of the 18bit by 18bit multiplier and a 36bit value is calculated. Because the resulting value of x*y in LabVIEW is of I16 data type, only the first 16 bits of the multiplier output are actually used in the block diagram and the remaining 20 bits of the result remain unwired and are essentially lost. If multiplying the two 16bit inputs, x and y, produced a value that was larger than 65536 (2^{16}) the 16bit output would overflow and produce incorrect results. This potential for overflow is important to note because it can introduce issues that that are extremely difficult to troubleshoot.
You might have already encountered errors caused by overflow and needed a way to account for the all 32bit possibilities when multiplying 16bit numbers. There are two ways to avoid overflow in this example. The first is to convert each number to 32bit integer values before multiplying, resulting in a full 32bit output.
Figure 7. Converting to I32 Data Type to Avoid Overflow
Instead of only using the first 16bits of the multiplier's 36bit output, this approach will use the first 32bits, and account for all possible output values.
The second, and more efficient, solution is to use the new fixedpoint numeric data type. Even though you might be working with integer numbers and no fractional values, fixedpoint math operations are helpful for managing precision and overflow.
Figure 8. Converting to FixedPoint Data Type to Avoid Overflow and Optimize Usage
By changing the I16 data type to a <±,16,16> fixedpoint data type, you can ensure that the multiply operation automatically grows the output data type to <±,32,32>. This means that you can use all 32 bits of the fixedpoint number to represent the integer part of the number. With fixedpoint, you also can maximize the inputs of FPGA multipliers with nonstandard bit widths like 18bit and 25bit.
For a refresher on how fixedpoint math works, please see the following IP Corner articles:
IP Corner: The LabVIEW FixedPoint Data Type Part 1 – FixedPoint 101
IP Corner: The LabVIEW FixedPoint Data Type Part 2 – Working with FixedPoint
3. Virtex5 DSP48E Slices
New FPGA architectures have further increased the performance of multipliers and even added other features specifically for digital signal processing (DSP). As mentioned earlier, the new Virtex5 family of FPGAs offers specialized multipliers called DSP48E slices. In addition to increasing the input sizes from 18x18 to 25x18, these new multipliers include accumulator circuitry to keep a running total of numbers being multiplied. This is also known as a multiply accumulate (MAC) function, and is a common building block for implementing DSP algorithms in hardware. The block diagram in Figure 9 shows how the multiplyaccumulate functionality looks in LabVIEW.
Figure 9. Graphical Representation of the Multiply Accumulate Function
However, the block diagram shown in Figure 9 does not actually produce an optimized function that uses the builtin accumulator circuitry. To take full advantage of DSP48E slices in LabVIEW FPGA, the compiler needs lowerlevel information on how to build an optimized circuit. Because of this, you can now download a highperformance DSP48E MAC function from IPNet that is specifically written for the Virtex5 resources using the advanced HDL node. This function comes complete with a simulation VI, so you can still verify the functionality of your application without having to compile.
Figure 10. DSP48E MAC Function (Available on IPNet)
See the following resources for more information:
4. Summary
Multiplication in FPGAs would be an expensive operation if it weren't for the prebuilt hardware multipliers on many of today’s targets. Highlevel programming tools such as LabVIEW FPGA make it easy to take advantage of multipliers without having to understand complex hardware design concepts while still providing ways to optimize for performance if necessary. Engineers and scientists can then focus on signal processing algorithms and meeting application requirements with new levels of customization.
For more information, please see the additional resources below.
5. Additional Resources
Learn More about FPGA Technology
IP Corner addresses issues and presents technical information on LabVIEW FPGA application reusable functionality, also known as FPGA IP. This article series is designed for those interested in learning, testing, or discussing topics to make FPGA designs better and faster through the reuse of IP.