Using Xilinx ISE to Prepare Verilog Modules for Integration Into LabVIEW FPGA

Publish Date: Nov 29, 2018 | 1 Ratings | 5.00 out of 5 | Print | 1 Customer Review | Submit your review


Two of the most commonly used hardware description languages are VHDL and Verilog. LabVIEW FPGA only supports native integration of third party IP written in VHDL. However, it is possible to integrate IP written in Verilog by following the procedures outlined in this tutorial.

This tutorial shows how to use Xilinx ISE Design Suite to prepare Verilog modules for integration into LabVIEW FPGA by using the following procedures:

  • Synthesize Design - convert the Verilog module into a Xilinx netlist (.ngc)
  • Create VHDL Simulation Model - generate a simulation model in VHDL
  • Create VHDL Wrapper - write a simple VHDL wrapper to instantiate the component

The attached file "" contains the tutorial (in PDF format) along with some example HDL files and a completed LabVIEW project.



  1. Download and extract "".
  2. Open "Preparing Verilog Modules For Integration Into LabVIEW FPGA.pdf" and follow the procedures.

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Customer Reviews
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Vivado  - Apr 5, 2016

Can NI also provide this example using Vivado instead of ISE?

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