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Offload Signal Processing With LabVIEW FPGA

Publish Date: Jun 15, 2017 | 6 Ratings | 3.33 out of 5 | Print | 1 Customer Review | Submit your review


Learn how to acquire and control FPGA I/O and functionally simulate your block diagram from the development computer before compiling it to run as a hardware circuit. This sample project takes DC measurements on analog data.

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Table of Contents

  1. Starting a New CompactRIO Project in LabVIEW
  2. Create a LabVIEW FPGA Application
  3. Explore the Desktop Testbench for FPGA Simulation

An FPGA is a high-performance, reconfigurable chip that engineers can program with LabVIEW FPGA tools. Traditionally, FPGA designers were forced to learn and use complex design languages such as VHDL to program FPGAs. Now, any engineer or scientist can use graphical LabVIEW tools to program and customize FPGAs. Using the FPGA embedded in NI reconfigurable I/O (RIO) hardware, you can implement custom timing, triggering, synchronization, control, and signal processing for your analog and digital I/O.


1. Starting a New CompactRIO Project in LabVIEW

Complete the tutorial below or download the attached sample code and open DC and RMS Measurement.lvproj to explore the code with the steps below.

Begin by creating a new project in LabVIEW to manage your code and hardware resources.

1. Create a new project in LabVIEW by selecting File»Create Project. Then select Blank Project.

2. The default project includes My Computer, which is where you can write code that runs on the Windows machine you’re currently developing on. Remember that a real-time target has a processor running a real-time OS, so it's effectively another computer. To write code that runs on that computer, you need to add another target to your project. Right-click on the Project item at the top of the tree and select New»Targets and Devices… to add a real-time system to the project.

3. With this dialog, you can discover existing systems on your network or add a new system. Select New target or device. LabVIEW lists available hardware corresponding with the drivers you have installed. Since you installed the NI-RIO driver with your evaluation software, select and expand Real-Time CompactRIO and then select cRIO-9074.


4. Save the project by selecting File»Save and entering DC and RMS Measurement. Click OK.

5. Right-click on the Chassis project item, named for the backplane of a CompactRIO target, and select New»FPGA Target. This puts the CompactRIO target in FPGA Interface Mode, so you can acquire I/O through an FPGA application.

6. If you had an existing system, LabVIEW would attempt to detect the I/O present in your system and automatically add it to the LabVIEW project. Since you are adding a new system, you need to manually add a C Series I/O module. To do this, right-click on the new FPGA Target project item and select New»C Series Modules…

7. In the same manner as the target, since you do not have physical hardware, select New target or device. Then select C Series Module and  click OK.

8. In the dialog box that appears, select an NI 9205 analog input module for Mod1 and then click OK.


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2. Create a LabVIEW FPGA Application

1. You should now have a new LabVIEW project that contains your CompactRIO system, including the controller, chassis, FPGA, and C Series I/O modules. Though you are using an NI 9205 analog input module in this tutorial, you can follow this process for any analog input module.

2. In the LabVIEW project, expand the CompactRIO real-time controller and chassis to find the FPGA item. Right-click on the FPGA item and select New»VI. This VI performs the high-speed analog acquisition and signal processing.

3. Save the VI as

4. To add an I/O node to acquire a sample from the analog input module, expand the folder named Mod1 and drag Mod1/AI0 to the FPGA VI diagram.


5. Expand the I/O node by clicking and dragging downward as shown, so that channels AI0 through AI3 are visible. This causes the I/O node to sample all four channels each time it executes.


6. Create indicators for each of the analog input channels.

7. Place four instances of the DC and RMS Measurements VI on the diagram and configure them for a DC measurement, calculated every 500 ms at an acquisition rate of 2 kS/s. This configures the VI to calculate the average value of the input samples each time a data set of 1000 samples is acquired.


8. The DC and RMS Measurement function returns a True value for the output valid? output each time an average is calculated and returned (when a data set of 1000 samples has been acquired). Place four Case structures on the diagram, create indicators for each DC result output, and use the output valid? Boolean output to control the Case structures as shown. This causes the indicators to be updated only when a valid result is available.


9. Enclose the code written so far in a flat sequence structure and add one frame after the code. Place a Loop Timer VI in the second frame and configure it for μSec timing. Wire a constant value of 500 to the Loop Timer. Finally, place a While Loop around the flat sequence structure and create a False constant for its stop condition.

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3. Explore the Desktop Testbench for FPGA Simulation

  1. When developing a LabVIEW FPGA VI, you should first simulate your design before compiling it to hardware. This saves development time and helps you ensure proper logic implementation and quickly iterate on your designs. To run your code in the simulation context, right-click the FPGA Target project item and select Select Execution Mode»Simulation (Simulated I/O).

2. Press the Run arrow to start the code and see the DC and RMS measurements with random I/O as the default inputs.

3. Since you are evaluating and do not have actual hardware, you simulate your design. Double-click to open the DC and RMS Measurement from your LabVIEW project.

Note the test bench is located under My Computer, so it runs on your desktop computer, exercises inputs into the FPGA logic, and reads outputs through the Desktop Execution Node. Since the test bench VI runs in the host context, you have access to hundreds of functions that you can use to create test vectors/cases/stimuli in addition to the checking, analysis, display, and reporting of test results.

4. The front panel is where you can change inputs that will be sent to your FPGA code and view the result.

5. Press <Ctrl-E> to view the block diagram. With the Desktop Execution Node, you can verify components of your FPGA logic. Right-click on the node and select Configure Desktop Execution Node….

6. Once you select your FPGA VI, all of the controls, indicators, and FPGA resources that you have access to populate under Available Resources. You can configure the Desktop Execution Node terminals by selecting the available resources of interest and using the blue arrows to copy them over into the Selected Resources window.

7. Clock ticks are taken from the Loop Timer input value in the FPGA VI. Since the VI in this application was configured in microseconds, 20,000 is the result of the following conversion: 40,000,000 Hz * 500 µs.The default onboard FPGA clock used here is 40 Hz.

8. Place your test bench to simulate the analog input values where indicated:

Next Steps in Design Flow

If you want to compile your design to run on FPGA hardware, you need to install the Xilinx Compile Tools. Set your VI back to hardware execution by right-clicking on FPGA Target in the project and select Select Execution Mode»FPGA Target. To start the compile, simply click the run arrow on your LabVIEW FPGA VI. 

After doing so, LabVIEW  prompts you to save your VI if you have not done so. LabVIEW then starts the process of translating your LabVIEW FPGA block diagram into native Hardware Description Language and generating the necessary files to start compiling. This process can take a little time. Note: Any changes you make to the FPGA VI after this point require a recompile.

Continue your Evaluation of LabVIEW with the LabVIEW RIO Evaluation Kit

Using the evaluation kit, develop an embedded system with the LabVIEW reconfigurable I/O (RIO) architecture. Use LabVIEW software and C/C++ to program NI RIO hardware, which includes a real-time processor, FPGA, and I/O. CompactRIO uses this same architecture for prototyping through deployment with a flexible array of configuration, expansion, and C Series module I/O options.


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Customer Reviews
1 Review | Submit your review

Default onboard clock should be 40 MHz  - May 24, 2014

RT, not 40 Hz

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