Example Code

migration-bot · ‎11-18-2020

Description

This document describes the example code for emulating a Linear Variable Differential Transformer (LVDT) sensor for HIL and other test applications using LabVIEW FPGA.

How to Use

1. Background and Scope

Engineers who design and test electronic modules that control aircraft, automobiles, and other systems often perform hardware in the loop (HIL) testing for validation and verification test.

One of the key elements of an HIL test system is the ability to emulate the sensor signals connected to the electronic module when it is deployed. By simulating environmental conditions at the sensor inputs, the testing process can verify the behavior of the control module under a wide variety of operating conditions, including conditions that would not be tested safely in the real world.

Figure 1. Sensor Emulation for HIL Application

A Linear Variable Differential Transformer (LVDT) is a sensor that uses a differential transformer with a sliding magnetic core to sense displacement. LVDTs are driven by an AC excitation source, typically a sine wave in the 1 to 10 kHz range, and generate an AC output signal that is proportional to the mechanical position of the core.

The output signals can be processed to recover the displacement value. Some LVDTs (referred to as DC LVDTs or DCDTs) have built-in excitation and demodulation circuitry that provides a DC output signal, but in most control applications the controller provides the excitation voltage and processes the raw LVDT output signals.

Emulating an LVDT takes some effort because the output signals are AC waveforms that are proportional to and in phase with the excitation signal provided by the controller. Traditional LVDT emulation approaches include:

Using a motion control system to position the core of a physical LVDT sensor.
Using a DSP processor and analog I/O circuitry to measure the excitation signal and synthesize the output signals.

LabVIEW FPGA can emulate LVDT signals with the performance and flexibility of a DSP processor without the complexity and development cost of an embedded DSP design.

2. The FPGA-based LVDT Emulator

Note: The following example is compatible with LabVIEW RIO devices that have both analog inputs and outputs.

This example acquires the LVDT excitation signal and calculates the corresponding output to emulate the LVDT displacement position. The output value is the product

V_o = simulated sensitivity * simulated displacement * latest excitation voltage measurement

Sensitivity is a constant value (specified in V/V/mm) and is a calibration constant for the specific LVDT to be emulated.

Note that the latency between the excitation measurement and output update introduces a small phase delay between the excitation and emulated signals.

3. Hardware Considerations

This example uses a single analog output to emulate an LVDT with a single output winding. To emulate an LVDT with a center-tap output, this example can be modified to use two analog outputs.

The excitation voltage is connected to one of the analog inputs, and the output voltage is generated on the corresponding analog output. The analog inputs and outputs operate up to ± 10 V (7 V_rms).

This article proposes 2 different methods to simulate LVDT.

4. Simple Method

Software Considerations

This example is divided into two parts: the FPGA VI and the host VI. The host VI, running on either Windows or a Real-Time target, performs a few floating point calculations and provides an API for rest of the application. The FPGA VI (shown below) runs on the FPGA and provides the instantaneous output response to rapid changes in the excitation signal. The following block diagrams only show one LVDT channel (single winding) for clarity.

Figure 2. LVDT Emulation FPGA VI

First, the excitation measurement (16-bit integer) value is multiplied by a 16-bit scaling factor. The resulting value is bit-shifted to form the output (16-bit integer) value to provide the desired scaling factor. As you will see, the bit-shifting compensates for a multiplying factor applied to the scaling factor on the host VI. This process provides the dynamic range within the integer math domain to support the flexibility and accuracy needed for most applications.

The emulation algorithm is pipelined using a shift register so that input and output (the performance limiting operations) can be performed in parallel. Note that the loop rate is dominated by the slower of the two operations and the total latency from input to output is the update period + the AO operation delay.

The host VI calculates and updates the scaling factor as the simulated displacement value changes. The scaling factor is the product of

SF = sensitivity * position * a scaling constant

The scaling constant in this example is 16384, or 2¹⁴, which corresponds to the negative 14-bit shift performed by the FPGA VI.

Figure 3. Scaling Factor Calculation in the Host VI

The example shown in the preceding diagrams uses a 14-bit logical shift in the FPGA VI and a scaling constant of 16384 in the host VI, which works for emulated LVDTs with a full-scale output-to-excitation ratio up to 2x, according to the table in Figure 3.

To calculate the full-scale output range and output ratio for a particular LVDT, use the following equations:

FS output V_rms = Excitation V_rms * simulated sensitivity * full scale sensor stroke
FS output ratio = simulated sensitivity * full scale sensor stroke

For example, if you emulate an LVDT with a stroke range of ±1.0 cm, a sensitivity of 45 mV/V/mm, and an excitation voltage of 3 V_rms, the full-scale output voltage (at +1 cm and -1 cm displacement) is the following:

1.35 V_rms = (3 V_rms ) * ((0.045 V)/V / mm) * (10 mm)

The full-scale output calculation is important for verifying that the output signal does not exceed the compliance range of the analog outputs.

Note: This calculation is only performed in one direction because for negative displacements, the output has the same magnitude but is 180º out of phase with the input.

The full-scale output ratio is the following:

FS output ratio = ((0.045 V)/V / mm) * (10 mm) = 0.45

To emulate this LVDT, use a bit shift of -15 and a scaling constant of 32768. This was determined using the table in Figure 3.

Host VI Example

The figure below shows a simple example of using the LVDT emulator in a host application. The LVDT emulator is controlled from a LabVIEW or LabVIEW Real-Time application by initializing the LVDT position and sensitivity variables, running the FPGA VI, and updating the simulated position as needed during the test (shown here within a loop).

Figure 4. Using FPGA-based LVDT Emulator in an Application

5. Advanced method

The second example relies on a different concept for each channel:

We measure period of the signal. Period measurement is done on 8 cycles to improve accuracy but keep a low latency response. Period measurement is performed in Ticks (number of 40 MHz cycles) and then used and converted to rate of phase change.
We measure the excitation signal. On same number of cycles (8) of incoming signal, we also perform a peak measurement of the signal (to scale Sensitivity of LVDT sensor to simulate).
Each new period of excitation signal, zero crossing instant is determined (in Ticks).
Using the zero cross and rate of change information from the excitation signal, we can compute the next point for LVDT simulation.

Figure 5. Waveform processing

On Figure 5, the detected sample-by-sample peak instant values (represented by red dots) are accumulated. Every 8 periods, the peak accumulator is divided by 8 and a peak value is obtained. This value is then scaled to match the Sensitivity requested by the user.

The detected sample-by-sample zero-crossing instant when gong from negative to positive is shown as the green dots in Figure 5. These three operations are performed by VI referred to "A." in the "AI Loop" in the example code. Figure 6 is a capture of the FPGA code diagram for illustration.

Figure 6. FPGA code block diagram

The sampling rate of our analog is usually not fast enough in order to detect the actual zero crossing. To increase accuracy, we need to use linear interpolation to calculate the zero crossing. As demonstrated in Figure 7, the equation between two acquired points "a" and "b" (white dots) is found and the zero crossing "t0" is calculated. This operation is performed by the VI labeled as "B." in Figure 6.

Figure 7. Zero-crossing instant

In the "AO Loop", the VI referred as "D" is actually responsible for elaboration of samples for next iteration. Per channel, it uses the rate of phase change information, the last zero crossing information, the scaled sensitivity, and the state of the excitation source (see below for explanation). There is a Lookup-Table of 16384 elements which contains one period of a sine signal. Based on a DDS technique, we determine the next sample index and scale its value using sensitivity information scaled by current excitation value. If the excitation is considered not present, then the output is forced to 0.0 V.

In code capture in Figure 6, the VI referred as "C" determines whether excitation is present or not. For that, we check that period measurement is in the [0.0001-0.01] s range. We also check that excitation peak value is greater than 1 V pk.

The code is designed to simulate 4 LVDTs but the same architecture can be replicated to accommodate number of LVDTs required. The example code includes a DDS generator in order to facilitate testing but is not mandatory. The code uses high-throughput math functions in order to perform different calculations. A host function is not provided, but can be easily added to define settings.

6. Performance Characteristics

To acquire performance characteristics of the methods, NI R Series devices were used. The methods described above can be used with any NI RIO device with analog input and output capabilities.

Method used	Simple	Simple	Advanced
	NI-783xR	NI-785xR	NI-785xR
Loop Rate	230 kHz	740 kHz	200 kHz*
Characteristics @ 3kHz excitation
Input-to-output phase difference	6 µSec	3 µSec	0.5 µSec
Samples per waveform cycle (AnaIog Input Part)	76.7	246	66.6*
Input-to-output phase delay	6.5 ^o	3.2 ^o	0.6 ^o
Input compliance	7 V_rms (±10V referenced to gnd)	7 V_rms (±10V referenced to gnd)	7 V_rms (±10V referenced to gnd)
Output compliance
Voltage	7 V_rms (±10V referenced to gnd)	7 V_rms (±10V referenced to gnd)	7 V_rms (±10V referenced to gnd)
Current	± 5 mA	± 2.5 mA	± 2.5 mA

* To illustrate the advanced method, for the tests, a PXI-7853R has been used, it can run Analog Inputs at 740KHz. On purpose, we chose to run Analog Inputs at lower frequency. It shows we can get good results (in terms of phase difference) without necessarily using the fastest Analog Inputs.

7. Comparison between methods

Advanced method advantages versus simple method

With that approach, the analog input rate and analog output rate are not necessarily the same. The faster the analog inputs, the better the accuracy of the simulation is.
Compared to first approach, input to output phase delay is really improved (reduced). Delay can be tuned.
Code is designed to simulate multiple (4) sensors. If more LVDTs have to be simulated, the code blocks can be duplicated.

Advanced method drawbacks versus simple method

We assume that excitation is stable. If frequency and/or amplitude vary significantly along time, it takes 8 periods to react.
If the excitation signal is not symmetrical, the simulated signal won’t reproduce that.
FPGA code is far more complex.

8. Feedback

This reference application was created by the NI Systems Engineering group.

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