LabVIEW FPGA Support for NI CVS-1450 Series Compact Vision System

Publish Date: Sep 06, 2006 | 7 Ratings | 3.43 out of 5 |  PDF | Submit your review


The NI CVS-1450 Series Compact Vision System provides 15 digital inputs and 14 digital outputs for controlling triggers, lighting, cameras, and other devices in a machine vision system. Digital I/O lines are available for TTL signaling as well as 5-30VDC isolated signals. The TTL I/O lines are often used for triggering a camera or strobe light, and the isolated I/O lines are commonly used to interface optical triggers, proximity sensors, relays, and other industrial devices. Three digital lines are conveniently available through SMB connectors on the front panel of the NI CVS-1450 Series, and the remaining lines are accessed through a standard 44-pin DSUB connector.

All digital I/O lines on the NI CVS-1450 Series are controlled by an onboard 1M gate FPGA running code built in LabVIEW FPGA. A default personality for the NI CVS-1450 Series is installed with NI-IMAQ for IEEE 1394 Cameras. This personality provides triggered pulse generation, quadrature encoder counting, product selection, static digital I/O, and other commonly used features. The features available in the default personality are suitable for a wide variety of machine vision applications. Like other National Instruments FPGA targets, such as the PXI-7831R, the NI CVS-1455 and NI CVS-1456 allow users to program the device using LabVIEW FPGA and define custom I/O functionality.

Table of Contents

  1. Requirements
  2. Hardware Installation
  3. Software Installation
  4. Creating a LabVIEW FPGA VI
  5. Using a LabVIEW FPGA VI in LabVIEW RT
  6. Frequently Asked Questions
  7. Examples

1. Requirements

The following list includes system requirements for using the LabVIEW FPGA Module with the LabVIEW Real-Time Module for ETS.
  • NI CVS-1455 or NI CVS-1456 Compact Vision System
  • LabVIEW Real-Time Module for ETS version 7.1
  • LabVIEW FPGA Module 1.1
  • NI-IMAQ for IEEE 1394 Cameras version 1.5.2 or later

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    2. Hardware Installation

If you are connecting to the NI CVS-1450 Series using a hub or switch, use a standard ethernet cable.

If you are connecting the NI CVS-1450 Series directly to the development PC, use a crossover ethernet cable.

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3. Software Installation

  1. Launch Measurement & Automation Explorer (MAX).
  2. In the configuration tree, expand Remote Systems, and select the device you want to configure.
  3. Expand the device, and select Software.
  4. Click Install Software.
  5. Select the following software to install:
    • LabVIEW RT 7.1 or later
    • NI 1450 RT 1.1.0 or later
    • NI-RIO 1.1.0 or later
    • NI-IMAQ for IEEE 1394 Cameras 1.5.2 or later
  6. Select any other software you want to install.
  7. Use the Next button to navigate through the remainder of the LabVIEW Real Time Install Software Wizard.

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    4. Creating a LabVIEW FPGA VI

Complete the following steps to create a LabVIEW FPGA VI:
  1. Launch LabVIEW
  2. Select FPGA Device (NI-1455, NI-1456 Compact Vision System) in Execution Target.
    Alternately, you can select the Compile Only option to develop a LabVIEW FPGA VI without connecting to a NI CVS-1450 Series.
    The following illustration shows the Compile Only option.

    Note: The NI CVS-1450 Series is required for executing the FPGA VI.

    Upon selecting the target, LabVIEW launches the Embedded Project Manager. When LabVIEW is already open and targeted to an FPGA device, click Tools»Embedded Project Manager to launch the Embedded Project Manager.

    In the Embedded Project Manager dialog box, click Project»Add to Project to add existing VIs to the project or create a new VI.
  3. After building the FPGA VI, click Run to compile and run the VI. If you selected a NI CVS-1450 Series as the execution target, the VI is downloaded automatically. If you selected the Compile Only option, the resulting compiled VI is stored on the host machine but is not executed.

    Tip: Examples of LabVIEW FPGA VIs are provided with the FPGA module, and more examples are available on the NI Developer Zone.

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    5. Using a LabVIEW FPGA VI in LabVIEW RT

Communication with the FPGA is handled through the LabVIEW RT application. Complete the following steps to use an FPGA VI in LabVIEW RT:
  1. Launch LabVIEW.
  2. In Execution Target, select the RT target by name or IP address.
  3. Create a new, blank VI and place the Open FPGA Reference VI on the diagram.
  4. Right-click the VI and choose Select Target VI to select the FPGA VI that you compiled previously. The FPGA VI is automatically downloaded to the NI CVS-1450 Series by the Open FPGA Reference VI when the application is executed.

    The output of this VI is a Hardware Execution Reference, which is passed to the Read/Write Control VI and the Invoke Method VI.

    Use the Read/Write Control VI to update parameters or pass data to and from the FPGA VI.

    Use the Invoke Method VI to programmatically download, run, or abort the FPGA VI.
  5. When you are finished communicating with the FPGA, use the Close FPGA VI Reference to end the session.

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    6. Frequently Asked Questions

The following sections include common questions regarding using LabVIEW FPGA Module with LabVIEW RT.

How can I incorporate the functionality of the default personality into my FPGA code?

The default personality that ships with the NI CVS-1450 Series consists of several code blocks which provide various functions. Incorporate these blocks into your FPGA VI to reuse some or all of the features of the default personality. The features you can include will depend on available space on the FPGA. The default personality that ships with the NI CVS-1450 Series consists of the following code blocks, which provide various functions:

  • 32-bit Quadrature Encoder
  • Six pulse generators
  • Product selection port
  • Watchdog timer
  • Enables block
  • TTL and ISO static output
  • TTL and ISO static input

Note: The pulse generator code block depends on the encoder count variable defined in the 32-bit quadrature encoder block. Make sure to include the encoder block with your VI if you use the pulse generator, or remove this section of the pulse generator block if you do not need to use encoder counts for the timebase.

Why does the FPGA VI not run when I start the RT application?

Two execution options are available in the properties for the Open FPGA Reference VI. You can select to open and run the VI or just open it. If you select to open the VI only, use the Invoke Method VI to start execution of the FPGA VI.

How long does it take to compile a VI using LabVIEW FPGA

Compiling the VI into a form that can run on the FPGA is a very computationally intensive operation. On a fast PC, a simple VI may take a few minutes to compile, while a large VI that fills most of the FPGA could require more than ten minutes. This delay can be largely mitigated by running the LabVIEW FPGA compile server on a machine other than the development system, which allows you to keep working on other tasks without slowing down the system.

How large of a VI can I fit in the FPGA?

The NI CVS-1455 and NI CVS-1456 each have a 1M gate FPGA. Estimating if a VI will fit in the FPGA requires some iteration. You can compile sections of a VI in small pieces to get an idea how much space the entire application requires. Although the amount of space required for a VI will not exactly match the sum of the parts, it's possible to get an estimate. Upon completion, the compile server returns several metrics that show the FPGA resources used. In general the number of SLICEs used is a good indicator of the required space.

What is the purpose of the TTL_EN_xx inputs?

The TTL_EN_xx inputs are used to control the enabled stated of the TTL lines. Use the enable control to tri-state the TTL lines when you do not want to drive them. Use the TTL lines as open collector outputs by driving a line low and toggling the enabled state. Depending on the requirements of your application, you can use the TTL lines either as TTL or as open collector.

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7. Examples

The following examples demonstrate several features from the default NI CVS-1450 Series personality. You are not restricted to using the same I/O lines shown in the sample code. For example, the quadrature encoder input in the default personality uses ISO_IN_06 and ISO_IN_07 for the input phases. If isolation is not required for the application, you can use the TLL input lines for the encoder. The TTL I/O lines can change state much faster than the ISO lines, which allows for higher pulse rates.

The examples discussed in the following sections are available for download from the NI Developer Zone at

Reading a Quadrature Encoder

The following block of code demonstrates reading a quadrature encoder. Position measurements from an encoder are often used to control other I/O operations that depend on position. For conveyor and assembly line operations, the encoder can be used as a timebase for pulse generation to account for speed variations in the line.

Static Input

Use the digital lines for static I/O when precise timing is not required. When the digital lines are used for static I/O, you will still benefit from the accuracy and determinism of the LabVIEW RT application setting the line state.

Watchdog Timer

A watchdog timer is useful in real time processes to ensure that a specified event occurs at regular intervals. If the event does not occur within the allotted time, the timer generates a signal that indicates an error condition.


You also can use the digital I/O lines to emulate standard digital communication protocols. Refer to the NI Developer Zone for an example program that performs serial communication using the RS-232 protocol.

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