Output Voltage Level Testing Technical Details (VOH, VOL)

Publish Date: Jun 13, 2018 | 19 Ratings | 4.42 out of 5 | Print | 1 Customer Review | Submit your review

Table of Contents

  1. Section 1: Hardware Setup
  2. Section 2: Software Setup


This document will discuss the technical details of testing the voltage output thresholds of digital semiconductor devices using a test system created using the PXI platform. To learn more about the hardware components of this test system, click here. To learn more about the software components of this test system, click here

Voltage output testing can be conducted on a wide range of devices from digital semiconductor chips to fully integrated consumer electronics devices. This paper will describe, in detail, the process of testing the voltage output levels on a packaged semiconductor chip. While voltage levels can be tested simply by using a high-impedance measurement device such as DMM, a more rigorous test can be performed by loading the outputs, yielding a more accurate depiction of a device’s functionality during normal loading conditions. This paper will describe such a test using a PXIe-4141 Source Measure Unit being used as the load as well as the measurement device.

1. Section 1: Hardware Setup

The essential connections for performing voltage output tests using this PXI system are relatively simple. The PXIe-414x SMU must be connected to VDD and VSS. Again, test engineers have the option here to decide to use the PXIe-6556's PPMU capabilities or to use the PXI-2535 to connect the SMU channels to the digital pins tested.

Figure 2: Test Setup for Voltage Output Levels

For a voltage output high (VOH) test on a particular pin (as shown above), the pin under test must first be conditioned to a logic-high output state. Then, the SMU can be used as a constant-current load on that pin to simulate the current loading of another digital device in the chip's final environment. Typically values of load current vary from hundreds of microamps to tens of miliamps. To simulate such a load, the SMU is set to sink the desired current and then measure the resulting voltage. Using an SMU to act as a load allows for accurate testing of voltage outputs at a variety of constant current loading conditions, or even to characterize the output voltage as a function of load current by performing a sweep. Pins that cannot source enough current to keep up with the load will have significantly lower output voltages, so measuring the voltage output level indicates weak or faulty output circuitry.

Voltage output low (VOL) tests are performed with the identical hardware configuration. The only differences are that pin under test must be preconditioned into the logic-low state, and the SMU must be set to source current into the chip to simulate another chip's pin driving circuitry. Pins that cannot sink enough current will have their voltage output low value significantly higher than 0 V (or VSS). In this manner, the voltage output levels, and in turn the health of the output transistors, on each digital pin can be tested.

Automated Test Steps

Step 1: Power the DUT by applying VDD

To power the DUT, the PXIe-4141 SMU should be configured to output the rated voltage of the device (usually 3.3 V). Setting a current limit is highly recommended to prevent damage to the DUT.

Step 2: Condition the DUT outputs to the logic-high state

For a VOH test, each pin to be tested must first be set to be an output (if it is bidirectional) and to be in the logic-high state. Similarly, for a VOL test, each pin to be tested must first be set to an output logic-low state. The PXIe-6556 is the ideal instrument for this test with custom digital voltage levels and built-in PPMU.

Step 3: Set the SMU to sink a small current (VOH), or source a small current (VOL)

For a VOH test, the SMU must act as a constant-current load, and for a VOL test, the SMU must act as a constant-current source. Before any pin is connected, the SMU should be set to source or sink the desired current, then, once the pin under test has been connected a voltage measurement should be performed.

Step 4: Connect the DUT pin to be tested

For an automated test system, tens or hundreds of pins must often be tested for voltage output levels, making high-density switching a necessity. In this system, a PXI-2535 FET Matrix Switch is used to provide connectivity to up to 136 pins. Since steps 1, 2 and 3 condition the device under test as well as the SMU into the appropriate state, switching to the pin under test will put the system in a measurement-ready state.

Step 5: Measure the output voltage

Measuring the output voltage then yields the pin's voltage output level under the specified loading conditions. For a more detailed characterization, the load current can be swept through a list of values.

Step 6: Switch to the next pin and repeat

Repeat steps 4 and 5 for each output pin under the device under test and pass the results out as an array for easy analysis.

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2. Section 2: Software Setup

For simplicity, only the voltage output high (VOH) parameter is tested in the code shown below. The software for this voltage output test was developed using NI LabVIEW and NI Switch Executive. LabVIEW is used as the primary Application Development Environment (ADE) while Switch Executive is used to configure routes on the high-density matrix.

The following software versions were used to implement the tests:

LabVIEW 8.5 Graphical Programming Environment

Switch Executive 2.1.1 Switch Management Software

The LabVIEW code described in this document can be downloaded from the link at the top of this document.

Note: Functional blocks in the LabVIEW graphical programming language are known as ‘Virtual Instruments’ or ‘VIs’. The acronym ‘VI’ will therefore be used when describing procedures in this section.

The following steps assume that a SMU will be used to measure voltage output levels using a PXI-2535 to increase channel count.

Step 1: Initialize the PXIe-4141 based on the resource name, then set the utility channel to power your device by changing the voltage set point to the desired VDD. Also remember to set the current limit to the max allowable current in order to protect your device and test setup. Once all settings are configured, enable the output of the utility channel in order to provide power to the device under test.

Step 2: If necessary, add digital I/O code to condition your device under test into the appropriate logic state such that all pins to be tested are configured as outputs in the logic-high state. This will allow a VOH test to be performed on those pins.

Step 3: Set the SMU to draw a small negative current to act as a load for each output pin under test. The output voltage will then be measured and listed for each pin in future steps.

Step 4: Initialize a session to the matrix switch via NI Switch Executive. The NI Switch Executive (NISE) Virtual Device Name is input to the Open Session VI to begin communication with all the switches in the system. The individual routes to each pin on the device under test are retrieved from the route group specified, and used later to make the connections. To download the "extract_routes" subVI and an example NI Switch Executive configuration, return to the software components section of this reference architecture.

Step 5: For each pin on the device under test (as specified by each route in the route group), make a connection to the pin, then perform a voltage measurement on the SMU  to measure the output voltage. Since the SMU was set to sink a small current in step 3, each voltage measurement will reflect the pin’s performance under normal loading conditions. Once this measurement has been taken, disconnect from the pin and repeat the process on the next.

Step 6: Show a histogram of the pin measurements and display the individual values in table.

Step 7: Disable the output of the PXIe-4141 and close the SMU instrument session.

Step 8: Disconnect all switch channels and close switch session.

The front panel of the attached example code allows the user to control the settings of the SMU and HSDIO instrument along with reading back the measured current draw of the device.

To add tests for VOL, incorporate additional steps to this code to condition the DUT to have logic-low outputs and the SMU to source current instead of sinking current. Then repeat the process of switching to each pin and measuring the voltage.

Additional Resources

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Customer Reviews
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Typo-Error in the document  - Mar 6, 2011

Hi, For Voltage Output Low, VOH is mentioned instead of VOL, please correct the same Regards Nagarajan P S

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