Power Consumption Testing Technical Details (IDD, IDDQ)

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Table of Contents

  1. Section 1: Hardware Setup
  2. Section 2: Software Setup


This document will discuss the technical details of testing the power parameters of semiconductor devices using a test system created using the PXI platform. To learn more about the hardware components of this test system, click here. To learn more about the software components of this test system, click here

Power consumption tests can be conducted on a wide range of devices from discrete components to semiconductor chips to fully integrated consumer electronics devices. This paper will describe the process of testing the power consumption on a packaged semiconductor chip. Power Consumption tests are performed by monitoring IDD, the amount of current that flows into the VDD terminal of a CMOS chip. As VDD is generally how power is supplied to the entire chip, measuring the IDD and multiplying by the VDD will result in the power consumption of the chip. Then, this power consumption can be used to make important distinctions about the characteristics of a device during validation, as well as the quality of a device during production test.

1. Section 1: Hardware Setup

The essential connections for performing power consumption test using this PXI system are relatively simple - the PXIe-414x SMU must be connected to the VDD and VSS terminals of the chip, and the PXIe-6556 must be connected to the communication lines on the chip to condition it into the appropriate state.

Figure 1: Testing for Power Consumption

By measuring the current draw from the VDD terminal of the device (the IDD), we can calculate the power consumption as:

Power Consumption = VDD * IDD

If the power measured is higher than expected, it is indicative of a short-circuit or resistive fault in the internal circuitry of the chip. On the other hand, if the power consumption is lower than expected, it is indicative of a non-functional chip. Power consumption tests are usually performed near the beginning to eliminate defective devices. The limits for these tests are highly dependent on the state that the device is set to.

Power consumption tests are essential for establishing the proper operation of a chip in a variety of states including:

  • After DUT reset, which checks for Gross IDD, the first test to verify overall functionality.
  • In standby mode, which checks for Static IDD to character power consumption in off or inactive mode. Measured currents can be under the µA level for this test.
  • In multiple quiescent logic states, which checks for IDD more rigorously in low power performance states. Again, measured currents can be under the µA level for this test.
  • While active, which checks for Dynamic IDD, the operating power.

If the device is drawing too much power in any of these states, that’s a big clue that there’s a structural issue inside the chip, and that it should not be used in a final environment as it has the potential to damage other components. As can be seen from this set of tests, the SMU in this scenario must act as a constant voltage source while measuring the current draw, which can be down to nA-level for static and IDDQ tests and up to 100 mA for dynamic tests. Here, the flexibility and precision of the PXIe-4141 SMU are important benefits.

Automated Test Steps

Step 1: Power the DUT by applying VDD

To power the DUT, the PXIe-4141 SMU should be configured to output the rated voltage of the device (usually 3.3 V). Setting a current limit is highly recommended to prevent damage to the DUT.

Step 2: Condition the DUT into the appropriate state

Because the power draw can be affected by the state of a device, it is essential that the device is preconditioned to a known state prior to the power being measured. This preconditioning is performed by using the PXIe-6556 HSDIO device because of its digital and PPMU capabilities.

In the case of a Gross IDD test, a conditioning pattern is not necessarily needed. To save time, power can be tested immediately after voltage is applied to the DUT in order to get a general idea of the device's consumption. In other cases, a reset pattern can be used.

Depending on the device, Dynamic IDD tests can require continuous patterns to be applied in order to keep the device active through constant stimulation. In this case, the power must be measured while the conditioning pattern is being applied.

In the case of an IDDQ test, multiple conditioning patterns can be applied sequentially, and power is measured after each step. These patterns are designed to keep the device in a low-power or quiescent state while still activating and changing internal logic sections.

Step 3: Measure the Current

The next step is to measure the current draw of the VDD terminal using the SMU. It is important to consider the range and the resolution needed on the expected current measurement. For instance, a static IDD measurement can result in currents at or below 1 µA, so it is important to use the SMU's lower ranges to achieve the necessary precision. In this case, the PXIe-4141 can be set to its lowest range of 10 µA in order to achieve 10 pA current measurement sensitivity. Some devices may also have an associated settling time before the current draw stabilizes, so a delay can also be necessary prior to measuring.

Step 4: Calculate Power and Evaluate

The final step is to convert the measured current into an associated power draw and compare that to the acceptable limit for a functional device. These limits are both device dependent and state dependent.

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2. Section 2: Software Setup

The software for this power consumption test system was developed using NI LabVIEW as the primary Application Development Environment (ADE).

The following software version was used to implement this Power Consumption Test:

LabVIEW 8.5 Graphical Programming Environment

The LabVIEW code described in this document can be downloaded from the link at the top of this document.

Note: Functional blocks in the LabVIEW graphical programming language are known as ‘Virtual Instruments’ or ‘VIs’. The acronym ‘VI’ will therefore be used when describing procedures in this section.

The software steps to test the current draw are as follows:

Step 1: Initialize the HSDIO instrument based on the resource name, then configure the channel List, clock Rate, and clock output terminal to satisfy your communications requirements. Make sure that the channel list accurately corresponds to the signals that are connected to the digital I/O interface on your DUT.

Step 2: Initialize the SMU based on the resource name, then set the voltage ouput level and current output limit needed for powering the DUT. Then, enable the output on the SMU to apply power.

Step 3: Write digital data into the HSDIO instrument that will condition the DUT to the desired state to be tested. Then, initiate the generation and wait until the pattern is finished generating.


Step 4: Measure the current consumed by the DUT using the SMU. The result is the IDD for the current state of the DUT.


Step 5: Disable the output of the SMU and close the session.

Step 6: Close the HSDIO instrument session and handle any errors.

The front panel of the attached example code allows the user to control the settings of the SMU and HSDIO instrument along with reading back the measured current draw of the device.

Additional Resources

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