Best Practices: Verifying Footprint Mappings and Landpattern Dimensions in NI Multisim and Ultiboard

Publish Date: Mar 30, 2010 | 2 Ratings | 4.00 out of 5 | Print | Submit your review

Overview

NI Multisim and NI Ultiboard provide an integrated platform to design, simulate, layout and prototype Printed Circuit Boards (PCBs). Designs can be easily transferred from the Multisim schematic environment to Ultiboard layout, ensuring consistency in your design with accurate land patterns and pin mappings.  Furthermore, the Forward and Backward Annotation system makes it intuitive to track and control footprint and mapping changes when synchronizing schematic with layout.

Best practices in design dictate verifying the symbol-to-footprint mappings and land pattern dimensions before transferring a design from Multisim to Ultiboard.  This tutorial describes how to verify these attributes using the LT1077S8 operational amplifier (op-amp) as an example.  Verification of footprint mappings and land pattern dimensions provide increased confidence in a board design before fabrication. By following such best practices, you will ultimately avoid unnecessary prototype iterations, saving time and money.

The following resource is one in a number of technical resources that have been created to guide engineers new to layout and design through the prototyping process. Please note that this tutorial assumes a basic understanding of the Multisim and Ultiboard environments.

Table of Contents

  1. Multisim Component Overview
  2. Step 1: How to Verify Footprint and Symbol-to-Footprint Mappings in NI Multisim
  3. Step 2: How to Verify Land Pattern Dimensions
  4. Conclusion

1. Multisim Component Overview

Components in Multisim consist of a symbol (for schematic capture), model (for simulation), and footprint (for PCB layout).  The footprint maps to a land pattern in Ultiboard, which is the conductive pattern that the component attaches to on the PCB. This land pattern effectively maps electrical signals to the pins of a semiconductor device (for example, a resistor or an op-amp).  

Figure 1: Symbol in Multisim (left) and land pattern in Ultiboard (right)

Figure 1 above shows the representation of a symbol in Multisim, which is used for schematic capture and simulation, and a land pattern in Ultiboard, which is used for PCB layout.  Figure 2 below shows the 3D view of a part in Ultiboard.  This image shows the footprint (the physical package defined by the manufacturer), and the land pattern (the copper pads below the package pins that serve to connect routed signals to the device).

Figure 2: 3D View of a part in Ultiboard

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2. Step 1: How to Verify Footprint and Symbol-to-Footprint Mappings in NI Multisim

The first step is to verify the component’s footprint, including the symbol-to-footprint mapping of the pins.  Both are extremely important steps to avoid the production of bad boards, and should not be overlooked.

  1. In Multisim, place the LT1077S8, by selecting Place > Component
  2. Navigate to the Analog Group, and select the OPAMP family

Figure 3: The Select a Component dialog

  1. In the Component field, enter LT1077S8, and select OK
  2. Left-click on the schematic to place the component
  3. Double-click on the component in your schematic, and select Edit footprint

Figure 4: The Edit Footprint, which displays the footprint and symbol-to-footprint mapping

  1. Using the datasheet for the LT1077 as a reference, verify that the LT1077S8 is mapped to the correct footprint.  In this case, the datasheet indicates that the component uses an SO 8-lead (S8 Package), which is consistent with the footprint that it is mapped to in Multisim
  2. Verify that the symbol-to-footprint mapping is consistent with the pin-out found in the datasheet

LT1077S8.JPG

Figure 5: Footprint information derived from the datasheet

We have now verified the footprint mapping and symbol-to-footprint pin-out for this component in Multisim, which will ensure that our net connections will transfer to Ultiboard properly.

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3. Step 2: How to Verify Land Pattern Dimensions

After verifying the component’s footprint and symbol-to-footprint mapping, the next step is to verify the land pattern dimensions in Ultiboard to ensure that the land pattern is sized correctly.  Land patterns in Ultiboard have been created assuming a Nominal Material Condition as specified by the IPC.  These land patterns assume designs of median density, and produce nominal land protrusions.  If a design is higher-density (for example used in a portable or hand-held application), then the Least Material Condition should be used to produce minimum land protrusions.  Similarly, if the design is lower-density, or industrial-level, then the Most Material Condition should be used to produce maximum land protrusions.

  1. In Multisim, double-click on the component in your schematic
  2. Click on Edit Footprint
  3. Click on Select From Database from the Edit Footprint dialog, as shown in Figure 6 
  4. In the Select a Footprint dialog, find the SO-8(S8)

Figure 6: Click on Select from database to access the Select a Footprint dialog

  1. Scroll over to the Ultiboard footprint  column; this is the name of the land pattern in Ultiboard

Select a Footprint.JPG

Figure 7: The Select a Footprint dialog

  1. Open Ultiboard
  2. In Ultiboard, place the  SOIC127P600X175-, by selecting Place  > From Database
  3. In the Surface Technology > IC > SO family, search for the SOIC127P600X175-8N
  4. Click on Show Dimensions; the land pattern will be annotated with pad, pitch and pin span dimensions

Land Pattern Dimensions.JPG

Figure 8: Land pattern with dimension annotations

  1. To verify other information, such as assembly dimensions, click OK.  This will place the land pattern in your design, to allow for more detailed inspection

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4. Conclusion

Verification is an essential part of the design process to assure that pin mappings and land pattern dimensions are accurate based on manufacturer’s specifications. Following the above mentioned steps can save hours of re-work and prototype iterations by catching errors early on in the design process.

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