VXI TriggersThe VMEbus standards defined a high-performance bus for test systems, but it did not cover the issues of timing and synchronization. VXI extended the VMEbus standards to define a trigger bus and protocols for trigger acknowledgments. These lines can be used for beginning or ending an acquisition sequence, for automating a test sequence, or for communicating as a digital bus. Any device is capable of asserting or receiving triggers as long as the hardware is available to control or respond to these lines. VXI/VME devices can be synchronized through the use of the VXIbus-defined trigger protocols to improve system performance with little software development. Synchronization is fixed with a known propagation rate of only 2 ns between slots on the VXI backplane. The VXIbus specification does not specifically define how to use these lines, but does define protocols for acknowledging triggers. To enhance the VXIbus standards, National Instruments has designed an ASIC called the Trigger Interface Chip (TIC) to enhance the users ability beyond the VXIbus definitions to implement triggering, signal routing, counting, and timing. On the National Instruments Slot 0 controllers that use the TIC ASIC (MXI-2, embedded, and GPIB-VXI controllers), there are 10 general-purpose input/output (GPIO) lines that can route non-trigger signals to or from the controllers front panel. Three are preassigned to the external CLK10, Trig In, and Trig Out connectors.
Structure of the Trigger Bus There is an additional protocol that can be useful, although it is not presently defined in the Rev. 1.4 of the VXIbus Specifications, the semi-sync protocol. It is a useful protocol but was removed from an earlier specification due to some problems in defining it with regard to multiple acceptors. Only the first two VXIbus-defined protocols will be discussed in this document as the ASYNC protocol is rarely used.
On/Off or Start/Stop (STST) Trigger Protocol The On/Off protocol is exactly what it sounds like. When the trigger line is held low (On), the device can initiate its activity; when held high (Off), the device stops its activity. An example of this is a device which acquires and processes data while the source holds a trigger line low (On) and stops when the source raises the trigger line high (Off).
This protocols timing is very precise because it uses the 10 Mhz CLK10 signal to synchronize the On and Off signals. Also, the propagation delay between slots in a chassis is always 2 ns; this means that cards in any two slots can be synchronized to start at the same time because the delay can easily be calculated between the two slots.
Device A is the controller that sends out a start signal to the two devices, B and C. Device A sends out a start signal which is clocked in by the CLK10 rising edge. Since it takes 20 ns longer for the CLK10 signal to arrive at Device C, Device B can internally delay its trigger by 20 ns in order to synchronize its activities with those of Device C. This assumes that Device B has an internal delay capability.
Synchronous (SYNC) Trigger Protocol
For more information on triggers, refer to the VXI bus specifications and also to National Instruments Technical Note 040, Triggering with NI-VXI (165 KB PDF). |
