LabVIEW NXG 4.0 FPGA Module Known Issues

Publish Date: Oct 30, 2019 | 0 Ratings | 0.00 out of 5 | Print

Overview

This document contains the LabVIEW NXG 4.0 FPGA Module known issues that were discovered before and since the release of LabVIEW NXG 4.0 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

Known Issues

The following items are known issues in LabVIEW NXG 3.1 FPGA Module.

709263 Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application
731891 After software installation on LinuxRT targets, RIO server requires a manual restart or additional reboot
744863 Errors outside of Clock-Driven Logic can incorrectly refer to the source of the error as an Optimized FPGA VI.


ID Known Issue
709263

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Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application
Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application because the 'Rename and Update' dialog fails to automatically update the reference to use the new name.

Workaround: Manually point the Open FPGA VI Reference to the correct FPGA Application.

Reported Version: 3.0    Resolved Version: N/A    Added: 10/29/2018
731891

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After software installation on LinuxRT targets, RIO server requires a manual restart or additional reboot
If RIO server is enabled, remote FlexRIO devices may be targeted via the RIO server. After SW installation, this service is not fully configured and requires an additional reboot or manual restart to be fully setup.

Workaround: After the required reboot post SW installation, reboot your target again.
Alternatively, run the following commands to manually restart the service:
/etc/init.d/nirioserver stop
/etc/init.d/nirioserver start

Reported Version: 3.1    Resolved Version: N/A    Added: 05/20/2019
744863

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Errors outside of Clock-Driven Logic can incorrectly refer to the source of the error as an Optimized FPGA VI.
Some errors outside of Clock-Driven Logic can incorrectly refer to "Optimized FPGA VI" as the source of the error. One example is an un-initialized shift register on a For Loop.

Workaround: Double-click the error to be taken to the actual error source.
Reported Version: 4.0    Resolved Version: N/A    Added: 10/30/2019

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