NI PXIe-6386 and NI PXIe-6396 Supplementary Information and Caveats

Publish Date: Sep 24, 2019 | 0 Ratings | 0.00 out of 5 | Print

Overview

The purpose of this document is to provide more in depth information and context on the PXIe-6386 and PXIe-6396. These devices largely function the same as other X Series SMIO devices, but due to its 15MS/s/ch maximum sampling rate, there are some considerations that this document highlights.

Table of Contents

  1. Maximum Sample Clock Rate
  2. Minimum sampling speed of 20kHz
  3. 1st two samples when using an External Sample Clock are invalid with an Analog Input task
  4. Retriggering in DAQmx is not supported
  5. DAQmx Control Task, Commit on Multiple DAQmx Reads Causes Errors
  6. Start Trigger on Analog Input Task Causes Potential Data Corruption
  7. Reference Clock Sources
  8. AI Sample Clock Timebase
  9. Pause Triggers
  10. Hardware Timed Single Point (HWTSP)
  11. DSA Channel Expansion
  12. SCXI not supported
  13. Throughput Considerations

1. Maximum Sample Clock Rate

These modules can achieve 15MS/s/ch maximum if using an external sample clock. It should be noted that to achieve that maximum sampling rate a timing module will need to be used to generate the external clock. The bandwidth on a line such as a PFI line is not large enough to feed in an external clock at the maximum sample clock rate directly to the PXIe-6386 or PXIe-6396 module.

The maximum rate that can be achieved using the internal or backplane clock on these modules is 14.29MS/s/ch due to the divide down from 100MHz clocks.

 

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2. Minimum sampling speed of 20kHz

This issue may affect customers who are trying to channel expand with slow sampling devices. LabVIEW shipping examples may also throw errors if they have a default sample rate slower than 20kHz. To resolve this, increase the sampling rate to a value larger than 20kHz, and, if needed, the data can be post processed when correlating with a slower sampled task.

 

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3. 1st two samples when using an External Sample Clock are invalid with an Analog Input task

The ADC used in these products must always be running to prevent the first two samples being invalid. When you are using an internally generated clock the board handles this for the user. But when using an external clock the first two samples will be invalid.  

 

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4. Retriggering in DAQmx is not supported

The PXIe-6386 and PXIe-6396 will not have support for retriggerable AI tasks in the NI-DAQmx driver.

 

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5. DAQmx Control Task, Commit on Multiple DAQmx Reads Causes Errors

NI-DAQmx 19.5 and later driver versions have a fix implemented for this issue. If using an earlier version of the NI-DAQmx driver that includes support for the NI PXIe-6386/96 please consider updating. For those earlier versions, if a Task is explicitly committed and then started and stopped within a loop, only the first iteration of that loop will execute. All subsequent loops will error with a timeout or hardware failure.

Figure 1: Simple example of reproducing case

 

 

Figure 2: Timeout and Hardware Failure Errors

To work around this, it is recommended that the task is reconfigured for each read. This can be achieved either by deleting the control task vi, or explicitly reserving the task instead.

 

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6. Start Trigger on Analog Input Task Causes Potential Data Corruption

NI-DAQmx 19.5 and later driver versions have a fix implemented for this issue. If using an earlier version of the NI-DAQmx driver that includes support for the NI PXIe-6386/96 please consider updating. 

 

The NI-DAQmx 19.0 driver has a version of firmware (19.1.0f2) for the PXIe-6386 and PXIe-6396 which can cause data corruption. It is possible for this data corruption to occur if the firmware version is 19.1.0f2. However, if you have firmware version 19.1.0f5 or newer the fix for this issue is implemented.

 

The 19.1.0f2 firmware issue occurs if the Start Trigger (Analog Edge, Analog Window, Digital Edge, etc) condition is met multiple times during the task, data corruption will occur at each trigger condition after the first Start Trigger. A sample will be dropped immediately after the trigger condition is met. In a finite task this will manifest as a timeout error, as not all of the requested samples will be available, but in a continuous task it will manifest as a dropped sample, but not throw any errors.

Figure 3: The issue appears as a dropped sample within the red circles

 

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7. Reference Clock Sources

These modules only have access to the PXIe_CLK100 and onboard clock for reference clock sources. A 100MHz oscillator is needed to derive the fastest sampling rates available for these modules.

 

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8. AI Sample Clock Timebase

AI tasks will not support using the 20MHz and 100kHz timebase. As a result the ai/SampleClockTimebase for these devices cannot use the 20MHz and 100kHz timebases in the NI-DAQmx driver. A 20MHz and 100kHz sample clock can be derived from other sources or imported from external sources including other NI devices. 

 

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9. Pause Triggers

AI tasks will not support pause triggering on these devices.

 

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10. Hardware Timed Single Point (HWTSP)

AI tasks will not support HWTSP on these devices.

 

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11. DSA Channel Expansion

Since DSA modules have specific timing needs, they provide their own default master timebase in channel expanded tasks. Since the PXIe-6386 and PXIe-6396 also have specific timing needs that the DSA modules cannot be programmed to accommodate, channel expansion with DSA modules is only supported for sampling rates up to 2.5MHz.

 

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12. SCXI not supported

The SCXI product line announced its EOL on Septempter 28th, 2018. These modules are being released after that EOL date and will not have support for the SCXI product line.

 

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13. Throughput Considerations

Due to the 15MHz maximum sampling rate, streaming applications or large finite acquisitions should consider the required throughput if they are using older PXI hardware.

In order to continuously transfer large amounts of data, the entire PXI Express system must be designed with sufficient data bandwidth. The PXIe-6386 and PXIe-6396 use a x4 PXI Express connection to the PXI Express chassis backplane. These modules will operate with a x1 connection, but the amount of data that can be sent to/from the host computer will be limited. Tasks using multiple channels at higher sample rates may experience buffer errors.

Additionally, the bandwidth between the PXI Express chassis and host computer can limit data throughput. When selecting a PXI Express embedded controller, make sure the controller specifies a sufficient per-slot bandwidth (for example, at least 500 MB/s slot bandwidth) and a sufficient system bandwidth to operate all devices installed in the system. If a PXI Express remote controller is selected, it should use a x4 or higher connection.  A x1 PXI Express remote controller does not have sufficient bandwidth to allow all channels to acquire/generate at maximum rates.

Example:
Maximum streaming rates:
PXIe-6396: 15MS/s x 8 ch x 32-bits = 480MB/s
PXIe-6386: 15MS/s x 8 ch x 16-bits = 240MB/s

For example, a NI PXIe-1078 chassis, the backplane architecture of which is pictured below, only has Gen-1 x1 PCI Express links from each slot. Slots 5-9 have Gen-1 x1 links back through a PCIe switch which has a Gen-1 x4 link to the controller. In either case, the actual link bandwidth of a slot is limited to 250MB/s, with possible further limitations on slots 5-9 depending on other modules sharing that PCIe switch.

Figure 1: PXIe-1078 Backplane Architecture

With the PXIe link’s theoretical bandwidth of 250MB/s, applications will not be able to get the throughput needed if streaming 8 channels from the PXIe-6396. Even when using the PXIe-6386, this will push the limitations of the chassis and may cause issues.

In contrast, the NI PXIe-1085 (24GB/s variant) has Gen-3 x8 PCI Express links from each slot to the Gen-3 PCIe Switches, which have Gen-3 x8 and Gen-3 x16 connections back to the controller slot. Choosing a chassis with this high of throughput, will allow for plenty of headroom for other modules or multiple PXIe-6386's or PXIe 6396's running at maximum rates without concerns of buffer errors. 

Figure 2: PXIe-1085 Backplane Architecture

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