FlexRIO Support 18.1 Known Issues and Bug Fixes

Publish Date: Jul 20, 2018 | 0 Ratings | 0.00 out of 5 | Print

Overview

This file contains important last-minute information about FlexRIO Support 18.1, including known issues.

1.  Known Issues

The following table contains the FlexRIO Support 18.1 known issues that were discovered before and since the release of FlexRIO Support 18.1. This table is not an exhaustive list of known issues; it is intended to show only the severe and common issues.

Each issue appears as a row in the table and includes the following fields.

  • Issue ID - The number in at the top of each of the cells in the first column. When you report an issue to NI, you may be given this ID, you can also find IDs posted by NI on the discussion forums or in Knowledge Base articles.  "N/A" indicates that there is no ID assigned to the issue.
  • Issue Title (in italics) - Describes the issue in one sentence or less.
  • Problem Description - A few sentences which describe the problem in further detail. The brief description given does not necessarily describe the problem in full detail, and it is expected that you may want more information on an issue. If you would like more information on an issue, contact NI and reference the ID number given in the document.
  • Workaround - Possible ways to work around the problem. The workarounds that appear in the document are not always tested by NI and are not guaranteed to resolve the issue. If a workaround refers you to the NI KnowledgeBase, visit www.ni.com/kb/ and enter the KnowledgeBase number in the search field to locate the specific document.
ID Known Issues
624455 Issue: In "NI 5783 - Getting Started" example, Data Clock setting is 125 MHz single frequency, which is inconsistent with x2 Data Clock (200 MHz).

Details: In "NI 5783 - Getting Started" example, Data Clock setting is 125 MHz single frequency, which is inconsistent with x2 Data Clock (200 MHz). This inconsistency leads to compile error when using some IPs which require Data Clock and x2 Data Clock for overclocking.

Workaround: Reload NI 5783 CLIP by disabling NI 5783 FAM and re-enabling NI 5783 FAM.
561398 Issue: FlexRIO example projects always search for CLIP in the Program Files (x86) folder, causing compilation to fail initially on 32-bit operating systems.

Details: The FlexRIO adapter module examples return a Missing CLIP implementation file error when compiling on a 32-bit OS. The LabVIEW project searches for the CLIP files for the adapter module in the C:\Program Files (x86)\National Instruments\ folder, which does not exist on a 32-bit OS.

Workaround: Open the IO Module properties page and click the Reload button in the General category.
545599 Issue: The Controller for FlexRIO (NI-793XR) does not support debugging FPGA VIs using a third-party simulator.

Details: The Controller for FlexRIO (NI-793XR) does not support the use of a third-party simulator to simulate and debug a LabVIEW FPGA VI.

Workaround: Open the IO Module properties page and click the Reload button in the General category.
526736 Issue: In the Streaming instrument design library, Wait For Stream.vi can return an incorrect value for the Samples Transferred output when an FPGA target is executed in Simulation mode.

Details: In the Streaming instrument design library, due to a race condition present only in Simulation mode, Wait For Stream.vi can return the second to last Samples Transferred value rather than the expected terminal value of a finite transfer.

Workaround: Do not use the Samples Transferred output from Wait For Stream.vi as the value for the Requested Elements input on a DMA FIFO when completing a finite transfer.
555601 Issue: DRAM on NI PXIe-797xR FPGA modules is inaccessible immediately after a download or reset of the FPGA.

Details: DRAM on NI PXIe-797xR FPGA modules is inaccessible immediately after a download or reset of the FPGA. A wait of at least 2.5 seconds must be added before before accessing the DRAM after an FPGA download or reset.

Workaround: After any reset or download of the FPGA, wait at least 2.5 seconds before accessing the DRAM.
596974 Issue: There may be one sample of uncertainty when synchronizing multiple NI 5752 or NI 5752B adapter modules.

Details: Due to a known issue in the constraints of the CLIPs for the NI 5752 and 5752B adapter modules there may be one sample of uncertainty when attempting to send the AdcTgcStart signal to the ADCs on the adapter modules. This may cause the gain sweep to start at different samples between adapter modules.
554346 Issue: The Aurora CLIP for the NI-793xR - MGT Aurora CLIP example may fail to initialize.

Details: A design using the Aurora CLIP from the NI-793xR - MGT Aurora CLIP example project may fail to initialize after downloading a bitfile or resetting the FPGA.

Workaround: Use the status signals on the Aurora CLIP to determine if an error occurred and re-download the bitfile until the CLIP initializes without an error.

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2.  Bug Fixes

The following table contains the IDs and titles of a subset of issues fixed in FlexRIO Support 18.1. This table is not an exhaustive list of issues fixed.

ID Fixed Issue
611161 Fixed an issue where assignment of IO module CLIP to IO module socket removes AuxIO CLIP from FPGA target.

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