LabVIEW 2018 FPGA Module Known Issues

Publish Date: Apr 04, 2019 | 0 Ratings | 0.00 out of 5 | Print

Overview

This document contains the LabVIEW 2018 FPGA Module known issues that were discovered before and since the release of LabVIEW 2018 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

The LabVIEW 2018 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.

Known Issues by Date

The following items are known issues in LabVIEW 2018 FPGA Module sorted by Date.

404665 The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
660205 When using the C API, some debugging tools may report a dynamic memory leak
673676 The compilation error "LabVIEW FPGA: Some of the compilation steps were not executed." can occur after upgrading to Windows 10 (version 1709) or later from an older version
684955 Certain FIFO configurations on Vivado targets will cause an error when compiling despite simulating without problem
693443 Incorrect Linux OS support listed in the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 installer
694049 Uninstalling LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 from NI Package Manager does not uninstall the LabVIEW FPGA and LabVIEW NXG FPGA Patch for Vivado 2017.2 on Windows 10
725737 Digital Output timing outside of Single-Cycle Timed Loops has extra delay



ID Known Issue
404665

Return
The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
According to the LabVIEW FPGA help documentation, the FIFO.configure method will clear the contents of the host-side FIFO buffer. This is not true if the FIFO.configure method does not change the "Actual Depth" of the host-side FIFO.

Workaround: Use FIFO.Stop and FIFO.Start to clear the host-side FIFO buffer.

Reported Version: 2012 SP1    Resolved Version: N/A    Added: 07/19/2013
660205

Return
When using the C API, some debugging tools may report a dynamic memory leak
When using the FPGA Interface C API, a memory leak may be reported by third-party debugging tools. This memory leak will only cause memory growth if the NiFpga_Initialize() and NiFpga_Finalize() functions are called continually or in a loop, and should not impact normal usage.

Workaround: Call NiFpga_Initialize() and NiFpga_Finalize() only once in the application, during the program initialization and exit procedures respectively.

Reported Version: 2017    Resolved Version: N/A    Added: 05/21/2018
673676

Return
The compilation error "LabVIEW FPGA: Some of the compilation steps were not executed." can occur after upgrading to Windows 10 (version 1709) or later from an older version
LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 has a known incompatibility with Windows 10 (version 1709) or newer. A patch for this issue already exists and ships with the installer, but is only installed if it detects that the version of Windows is Windows 10 (version 1709) or newer. If a system is upgraded to build 1709 after installing the Compilation Tool, the issue corrected by the patch will occur as the patch will not be installed.

Workaround: Run the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 installer after upgrading to Windows 10 (version 1709), or install the LabVIEW FPGA and LabVIEW NXG FPGA Patch for Vivado 2017.2 on Windows 10 from the NI Update Service.

Reported Version: 2018    Resolved Version: 2018    Added: 05/21/2018
684955

Return
Certain FIFO configurations on Vivado targets will cause an error when compiling despite simulating without problem
As of LabVIEW FPGA 2018, FPGA targets using the Vivado compiler no longer support the "Get Number of Elements to Read" and "Get Number of Elements to Write" nodes on FIFOs set explicitly to Built-in control logic. When compiling an error explaining this is correctly thrown. However, no error is thrown when simulating the FPGA code in this configuration.

Workaround: Remove the "Get Number of Elements to Read" and "Get Number of Elements to Write" nodes, or change the control logic of the FIFO.

Reported Version: 2018    Resolved Version: N/A    Added: 05/21/2018
693443

Return
Incorrect Linux OS support listed in the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 installer
When running the install script for LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 for Linux, the script will incorrectly report that the only supported Linux distribution is Red Hat Enterprise Linux Desktop + Workstation.

Workaround: Refer to the README.txt file included with the installer for the correct support information.

Reported Version: 2018    Resolved Version: N/A    Added: 05/21/2018
694049

Return
Uninstalling LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 from NI Package Manager does not uninstall the LabVIEW FPGA and LabVIEW NXG FPGA Patch for Vivado 2017.2 on Windows 10
When uninstalling the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 on Windows 10 (version 1709) or later from NI Package Manager, components specific to a patch for the compile tools will be left installed.

Workaround: Manually uninstall the patch's package from NI Package Manager after uninstalling the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2.

Reported Version: 2018    Resolved Version: N/A    Added: 05/21/2018
725737

Return
Digital Output timing outside of Single-Cycle Timed Loops has extra delay
In LabVIEW 2014 SP1 FPGA and earlier, using Digital Outputs outside of a Single-Cycle Timed Loop would result in the output taking only a single cycle of the FPGA Base Clock to execute. Currently this takes several additional clock cycles.

Workaround: Move Digital Outputs which have tight timing requirements into Single-Cycle Timed Loops.

Reported Version: 2015    Resolved Version: N/A    Added: 01/23/2019



Known Issues by Category

The following items are known issues in LabVIEW 2018 FPGA Module sorted by Category.

FPGA Interface C API
660205 When using the C API, some debugging tools may report a dynamic memory leak
Functions, VIs, and Express VIs
404665 The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
684955 Certain FIFO configurations on Vivado targets will cause an error when compiling despite simulating without problem
Installation and Activation
673676 The compilation error "LabVIEW FPGA: Some of the compilation steps were not executed." can occur after upgrading to Windows 10 (version 1709) or later from an older version
693443 Incorrect Linux OS support listed in the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 installer
694049 Uninstalling LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 from NI Package Manager does not uninstall the LabVIEW FPGA and LabVIEW NXG FPGA Patch for Vivado 2017.2 on Windows 10
Miscellaneous
725737 Digital Output timing outside of Single-Cycle Timed Loops has extra delay



ID Known Issue
FPGA Interface C API
660205

Return
When using the C API, some debugging tools may report a dynamic memory leak
When using the FPGA Interface C API, a memory leak may be reported by third-party debugging tools. This memory leak will only cause memory growth if the NiFpga_Initialize() and NiFpga_Finalize() functions are called continually or in a loop, and should not impact normal usage.

Workaround: Call NiFpga_Initialize() and NiFpga_Finalize() only once in the application, during the program initialization and exit procedures respectively.

Reported Version: 2017    Resolved Version: N/A    Added: 05/21/2018
Functions, VIs, and Express VIs
404665

Return
The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
According to the LabVIEW FPGA help documentation, the FIFO.configure method will clear the contents of the host-side FIFO buffer. This is not true if the FIFO.configure method does not change the "Actual Depth" of the host-side FIFO.

Workaround: Use FIFO.Stop and FIFO.Start to clear the host-side FIFO buffer.

Reported Version: 2012 SP1    Resolved Version: N/A    Added: 07/19/2013
684955

Return
Certain FIFO configurations on Vivado targets will cause an error when compiling despite simulating without problem
As of LabVIEW FPGA 2018, FPGA targets using the Vivado compiler no longer support the "Get Number of Elements to Read" and "Get Number of Elements to Write" nodes on FIFOs set explicitly to Built-in control logic. When compiling an error explaining this is correctly thrown. However, no error is thrown when simulating the FPGA code in this configuration.

Workaround: Remove the "Get Number of Elements to Read" and "Get Number of Elements to Write" nodes, or change the control logic of the FIFO.

Reported Version: 2018    Resolved Version: N/A    Added: 05/21/2018
Installation and Activation
673676

Return
The compilation error "LabVIEW FPGA: Some of the compilation steps were not executed." can occur after upgrading to Windows 10 (version 1709) or later from an older version
LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 has a known incompatibility with Windows 10 (version 1709) or newer. A patch for this issue already exists and ships with the installer, but is only installed if it detects that the version of Windows is Windows 10 (version 1709) or newer. If a system is upgraded to build 1709 after installing the Compilation Tool, the issue corrected by the patch will occur as the patch will not be installed.

Workaround: Run the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 installer after upgrading to Windows 10 (version 1709), or install the LabVIEW 2018 FPGA Module Patch for Vivado 2017.2 on Windows 10 1709 from the NI Update Service.

Reported Version: 2018    Resolved Version: 2018    Added: 05/21/2018
693443

Return
Incorrect Linux OS support listed in the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 installer
When running the install script for LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 for Linux, the script will incorrectly report that the only supported Linux distribution is Red Hat Enterprise Linux Desktop + Workstation.

Workaround: Refer to the README.txt file included with the installer for the correct support information.

Reported Version: 2018    Resolved Version: N/A    Added: 05/21/2018
694049

Return
Uninstalling LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 from NI Package Manager does not uninstall the LabVIEW FPGA and LabVIEW NXG FPGA Patch for Vivado 2017.2 on Windows 10
When uninstalling the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 on Windows 10 (version 1709) or later from NI Package Manager, components specific to a patch for the compile tools will be left installed.

Workaround: Manually uninstall the patch's package from NI Package Manager after uninstalling the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2.

Reported Version: 2018    Resolved Version: N/A    Added: 05/21/2018
Miscellaneous
725737

Return
Digital Output timing outside of Single-Cycle Timed Loops has extra delay
In LabVIEW 2014 SP1 FPGA and earlier, using Digital Outputs outside of a Single-Cycle Timed Loop would result in the output taking only a single cycle of the FPGA Base Clock to execute. Currently this takes several additional clock cycles.

Workaround: Move Digital Outputs which have tight timing requirements into Single-Cycle Timed Loops.

Reported Version: 2015    Resolved Version: N/A    Added: 01/23/2019

Document last updated on 4/3/2019

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