Features and Differences of NI Multifunction DAQ PFI Lines

Publish Date: Jul 30, 2018 | 1 Ratings | 1.00 out of 5 | Print

Overview

This article explains the features and differences of the Programmable Function Interface (PFI) Lines between NI Multifunction I/O (MIO) devices and modules including: NI 63xx (formerly X Series), NI 62xx (formerly M Series), NI 61xx (formerly S Series) and NI 60xxE (formerly E Series).

Table of Contents

  1. Introduction
  2. NI 63xx (formerly X Series)
  3. NI 62xx (formerly M Series)
  4. NI 60xxE (formerly E Series)
  5. NI 61xx (formerly S Series)
  6. Additional Resources

1. Introduction

Programmable Function Interface (PFI) lines have different functionality based on the series of Data Acquisition device you are using. For details, consult the device manual. A summary of functionality based on the series follows.

 

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2. NI 63xx (formerly X Series)


X Series devices have up to 16 PFI lines.  Each PFI line can be individually configured as the following:

  • Static Digital Input
  • Static Digital Output
  • Timing Input Signal for AI, AO, DI, DO, or counter/timer functions
  • Timing Output Signal from AI, AO, DI, DO, or counter/timer functions


Each PFI line can be individually configured as a static digital input or a static digital output. When a terminal is used as a static digital input or output, it is called P1.x or P2.x. On the I/O connector, each terminal is labeled PFI x/P1.x or PFI x/P2.x. The voltage input levels, voltage output levels, and current drive levels of the PFI line signals are listed in the specifications of your device.

PFI lines can also be configured to detect digital changes. The values on the PFI lines cannot be read in a hardware-timed task, but they can be used to fire the change detection event. For example, if you wanted to do change detection on eight timed DIO lines but wanted to ensure that the value of the lines was updated every second independent of the eight lines changing, you could set a PFI line up for change detection and connect a 1 Hz signal to it.

You can enable a programmable debouncing filter on each PFI, RTSI, PXI_STAR, or PXIe-DSTAR<A, B> signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. X Series devices use an onboard oscillator to generate the filter clock.

 

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3. NI 62xx (formerly M Series)


M Series devices have up to 16 PFI lines. Each PFI can be individually configured as the following:

  • Static Digital Input
  • Static Digital Output
  • Timing Input Signal for AI, AO, DI, DO, or counter/timer functions
  • Timing Output Signal from AI, AO, DI, DO, or counter/timer functions


Each PFI line can be individually configured as a static digital input or a static digital output. When a terminal is used as a static digital input or output, it is called P1.x or P2.x. On the I/O connector, each terminal is labeled PFI x/P1.x or PFI x/P2.x. Static I/O is basic digital I/O that employs no handshaking or hardware-controlled timing. Static I/O mode is interrupt driven, so it is relatively slow, allowing a maximum of about 10 kHz depending on your computer.

When a terminal is used as a timing input or output signal, it is called PFI x (where x is an integer from 0 to 15). When a terminal is used as a static digital input or output, it is called P1.x or P2.x. On the I/O connector, each terminal is labeled PFI x/P1.x or PFI x/P2.x. The voltage input levels, voltage output level, and current drive levels of the PFI signals are listed in the specifications of your device.

Measurement and Automation Explorer (MAX) offers Device Route tabs for M Series devices, which contains information on routes available. Additionally, you can enable a programmable debouncing filter on each PFI signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency.

 

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4. NI 60xxE (formerly E Series)


E Series devices have 10 PFI lines which can be configured as the following:

  • Timing Input Signal for AI, AO, or counter/timer functions
  • Timing Output Signal from AI, AO, or counter/timer functions


An external timing signal can be input on any PFI line and multiple timing signals can simultaneously use the same PFI line. This flexible routing scheme reduces the need to change the physical connections to the I/O connector for different applications. When using the PFI line as an input, you can individually configure each PFI line for edge or level detection and for polarity selection. You can use the polarity selection for any of the timing signals, but the edge or level detection depends upon the particular timing signal being controlled. The detection requirements for each timing signal are listed within the section that discusses that signal.

You can also individually enable each PFI line to output a specific internal timing signal. For example, if you need the Counter 0 Source signal as an output on the I/O connector, software can turn on the output driver for the PFI 8/CTR 0 SRC pin. This signal, however, cannot be output on any other PFI line.

 

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5. NI 61xx (formerly S Series)


S Series devices have 10 PFI lines which can be configured as the following:

  • Timing Input Signal for AI, AO, or counter/timer functions
  • Timing Output Signal for AI, AO, or counter/timer functions


As an input, each PFI line can be configured for edge or level detection, depending on the application signal variety (analog, counter). An external timing signal connected to a PFI line may be accessed simultaneously by multiple timing signals internally. This flexible routing scheme mitigates the need to change physical connections to the I/O connector between applications.

As an output, there is less flexibility in routing internal timing signals to PFI pins. For example, if you need the Counter 0 Source signal as an output, it may be accessed on the PFI8/CTR 0 SRC pin only. Internal timing signals that may be output to PFI lines are as follows:

  • AI Start Trigger Signal
  • AI Reference Trigger Signal
  • AO Start Trigger Signal
  • AO Sample Clock Signal
  • Counter 0 Source Signal
  • Counter 0 Gate Signal
  • Counter 1 Source Signal
  • Counter 1 Gate Signal

 

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6. Additional Resources

 

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