NI VeriStand 2017 Known Issues

Publish Date: Feb 15, 2019 | 0 Ratings | 0.00 out of 5 | Print

Overview

This document contains the NI VeriStand 2017 known issues that were discovered before and since the release of NI VeriStand 2017. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

Known Issues by Date

The following items are known issues in NI VeriStand 2017 sorted by Date.

317883 Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
383092 Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
386381 The Pulse Measurement task may return incorrect data
392092 Error -200452 occurs when a 433x device uses hardware timed single point
402293 Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
522678 Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
527148 Programmatic deployment of VeriStand Projects to password protected targets requires user interaction
372874 Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
572887 Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
581727 XNET Database deployment fails on password-protected target
590854 Not possible to disable the VeriStand workspace
468712 VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
654632 Models built in LabVIEW 2017 fail to deploy to RT PXI and cRIO-908x targets running NI VeriStand 2017
676011 Some Indicators May Behave as Controls in UI Manager 2017
678060 VeriStand UI Manager 2017 can crash if the time zone on the host is set to UTC + 6:30 or later.



ID Known Issue
317883

Return
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build

Workaround: Do not use % in the block name.

Reported Version: 2010    Resolved Version: N/A    Added: 10/09/2011
383092

Return
Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
Streaming a large number of waveforms to the waveform graph can cause the VeriStand gateway to be overwhelmed and stop responding in a timely fashion.

Workaround: Reduce CPU usage on the gateway computer or stream fewer waveforms.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
386381

Return
The Pulse Measurement task may return incorrect data
In certain configurations where the signal is disconnected or has a 0/100% duty cycle, the Pulse Measurement task may report invalid readings. The returned reading of the disconnected signal will be the last non 0/100% duty cycle processed by your device.

Workaround: Install NI DAQmx 9.7 drivers

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
392092

Return
Error -200452 occurs when a 433x device uses hardware timed single point
If a 433x device is set as the master or if there is only a 433x device in a system definition, using hardware timed single point will cause error -200452 to occur during deployment.

Workaround: Use at least one other device in the system definition

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
402293

Return
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN making it impossible to map to the channel correctly.

Workaround: Use the channel mappings dialog to import from a text file instead of using the dialog.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
522678

Return
Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
When using the System Definition API to programmatically add an FPGA target to a System Definition file, the Parameters section typically included with PWM channels is excluded.

Workaround: Add the FPGA manually to the System Definition via the System Explorer.

Reported Version: 2014    Resolved Version: N/A    Added: 08/13/2015
527148

Return
Programmatic deployment of VeriStand Projects to password protected targets requires user interaction
When deploying a VeriStand Project to a real-time target protected with a password a user is required to interact with a login dialog box. Consequently, programmatic deployment using the API still requires user interaction, preventing truly headless deployment.

Workaround: Have an operator interact with the dialog box or do not use password protected targets for programmatic deployments.

Reported Version: 2014    Resolved Version: N/A    Added: 08/13/2015
372874

Return
Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
When building a VI into a model for NI VeriStand, the build process will fail if any of the indicators or controls have identical names.

Workaround: Use different names for the controls and indicators that will become the model's inports and outports.

Reported Version: 2011 SP1    Resolved Version: N/A    Added: 08/18/2015
572887

Return
Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
As the Frame Type is pulled from the XNET database, this System Definition setting does not affect the XNET configuration.

Workaround: Set the Frame Type as desired in the XNET database. Do not use the Raw Data Frame Type Configuration option in the System Definition.

Reported Version: 2014    Resolved Version: N/A    Added: 04/01/2016
581727

Return
XNET Database deployment fails on password-protected target
When deploying a VeriStand system definition which contains an XNET database to a password-protected real-time target, the deployment fails, displaying the message, "File transfer communication with the LabVIEW Real-Time (RT) target failed."

Workaround: Deploy XNET database manually before using VeriStand to deploy the rest of the system.

Reported Version: 2015    Resolved Version: N/A    Added: 04/07/2016
590854

Return
Not possible to disable the VeriStand workspace
When UI Manager is used in a VeriStand project, both UI Manager and the Workspace are launched at execution time. There is currently no way to disable this.

Workaround: Launch your VeriStand project silently and then manually open UI Manager.

Reported Version: 2015 SP1    Resolved Version: N/A    Added: 06/08/2016
468712

Return
VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
If Slow Background Conversion mode is enabled on a DAQ card (like a PXIe-4353) and it's the first DAQ device listed in the system definition, VeriStand incorrectly tries to use this device as the master timing card. VeriStand will do this even if there are other DAQ cards running without Slow Background Conversion enabled.

Workaround: Add the DAQ card that you want to use as the master timing source to the system definition before adding the Slow Background Conversion DAQ card. If both cads are already in the system definition, remove and re-add the Slow Background Conversion-enabled card.

Reported Version: 2013 SP1    Resolved Version: N/A    Added: 06/14/2017
654632

Return
Models built in LabVIEW 2017 fail to deploy to RT PXI and cRIO-908x targets running NI VeriStand 2017
Deployment of a VeriStand project to RT PXI or cRIO-908x targets running NI VeriStand 2017 will fail when one or more models built in LabVIEW are included in the System Definition.

Workaround: Install the VeriStand 2017 f1 patch.

Reported Version: 2017    Resolved Version: 2017 f1    Added: 09/01/2017
676011

Return
Some Indicators May Behave as Controls in UI Manager 2017
In UI Manager 2017, it may be possible to update underlying channel values by editing the value of some types of indicators used on the screen as if they were controls.

Workaround: Do not modify these indicator values unless an update to the underlying channel value is desired.

Reported Version: 2017    Resolved Version: N/A    Added: 01/18/2018
678060

Return
VeriStand UI Manager 2017 can crash if the time zone on the host is set to UTC + 6:30 or later.
VeriStand UI Manager 2017 can crash if the time zone on the host machine is set to UTC + 6:30 or later when manually associating a UI Manager project with a VeriStand System Definition.

Workaround: Install the VeriStand UI Manager 2017 f1 patch or change the time zone on the host to UTC + 6:00 or earlier.

Reported Version: 2017    Resolved Version: UI Manager 2017 f1    Added: 04/17/2018


Known Issues by Category

The following items are known issues in NI VeriStand 2017 sorted by Category.

Miscellaneous
386381 The Pulse Measurement task may return incorrect data
392092 Error -200452 occurs when a 433x device uses hardware timed single point
676011 Some Indicators May Behave as Controls in UI Manager 2017
678060 VeriStand UI Manager 2017 can crash if the time zone on the host is set to UTC + 6:30 or later.
Model Interfacing
317883 Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
402293 Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
372874 Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
654632 Models built in LabVIEW 2017 fail to deploy to RT PXI and cRIO-908x targets running NI VeriStand 2017.
Performance
383092 Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
590854 Not possible to disable the VeriStand workspace
System Explorer
572887 Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
581727 XNET Database deployment fails on password-protected target
468712 VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
Using the API
522678 Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
527148 Programmatic deployment of VeriStand Projects to password protected targets requires user interaction



ID Known Issue
Miscellaneous
386381

Return
The Pulse Measurement task may return incorrect data
In certain configurations where the signal is disconnected or has a 0/100% duty cycle, the Pulse Measurement task may report invalid readings. The returned reading of the disconnected signal will be the last non 0/100% duty cycle processed by your device.

Workaround: Install NI DAQmx 9.7 drivers

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
392092

Return
Error -200452 occurs when a 433x device uses hardware timed single point
If a 433x device is set as the master or if there is only a 433x device in a system definition, using hardware timed single point will cause error -200452 to occur during deployment.

Workaround: Use at least one other device in the system definition

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
676011

Return
Some Indicators May Behave as Controls in UI Manager 2017
In UI Manager 2017, it may be possible to update underlying channel values by editing the value of some types of indicators used on the screen as if they were controls.

Workaround: Do not modify these indicator values unless an update to the underlying channel value is desired.

Reported Version: 2017    Resolved Version: N/A    Added: 01/18/2018
678060

Return
VeriStand UI Manager 2017 can crash if the time zone on the host is set to UTC + 6:30 or later.
VeriStand UI Manager 2017 can crash if the time zone on the host machine is set to UTC + 6:30 or later when manually associating a UI Manager project with a VeriStand System Definition.

Workaround: Install the VeriStand UI Manager 2017 f1 patch or change the time zone on the host to UTC + 6:00 or earlier.

Reported Version: 2017    Resolved Version: UI Manager 2017 f1    Added: 04/17/2018
Model Interfacing
317883

Return
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build

Workaround: Do not use % in the block name.

Reported Version: 2010    Resolved Version: N/A    Added: 10/09/2011
402293

Return
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN making it impossible to map to the channel correctly.

Workaround: Use the channel mappings dialog to import from a text file instead of using the dialog.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
372874

Return
Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
When building a VI into a model for NI VeriStand, the build process will fail if any of the indicators or controls have identical names.

Workaround: Use different names for the controls and indicators that will become the model's inports and outports.

Reported Version: 2011 SP1    Resolved Version: N/A    Added: 08/18/2015
654632

Return
Models built in LabVIEW 2017 fail to deploy to RT PXI and cRIO-908x targets running NI VeriStand 2017.
Deployment of a VeriStand project to RT PXI or cRIO-908x targets running NI VeriStand 2017 will fail when one or more models built in LabVIEW are included in the System Definition.

Workaround: Install the VeriStand 2017 f1 patch.

Reported Version: 2017    Resolved Version: 2017 f1    Added: 09/01/2017
Performance
383092

Return
Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
Streaming a large number of waveforms to the waveform graph can cause the VeriStand gateway to be overwhelmed and stop responding in a timely fashion.

Workaround: Reduce CPU usage on the gateway computer or stream fewer waveforms.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
590854

Return
Not possible to disable the VeriStand workspace
When UI Manager is used in a VeriStand project, both UI Manager and the Workspace are launched at execution time. There is currently no way to disable this.

Workaround: Launch your VeriStand project silently and then manually open UI Manager.

Reported Version: 2015 SP1    Resolved Version: N/A    Added: 06/08/2016
System Explorer
572887

Return
Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
As the Frame Type is pulled from the XNET database, this System Definition setting does not affect the XNET configuration.

Workaround: Set the Frame Type as desired in the XNET database. Do not use the Raw Data Frame Type Configuration option in the System Definition.

Reported Version: 2014    Resolved Version: N/A    Added: 04/01/2016
581727

Return
XNET Database deployment fails on password-protected target
When deploying a VeriStand system definition which contains an XNET database to a password-protected real-time target, the deployment fails, displaying the message, "File transfer communication with the LabVIEW Real-Time (RT) target failed."

Workaround: Deploy XNET database manually before using VeriStand to deploy the rest of the system.

Reported Version: 2015    Resolved Version: N/A    Added: 04/07/2016
468712

Return
VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
If Slow Background Conversion mode is enabled on a DAQ card (like a PXIe-4353) and it's the first DAQ device listed in the system definition, VeriStand incorrectly tries to use this device as the master timing card. VeriStand will do this even if there are other DAQ cards running without Slow Background Conversion enabled.

Workaround: Add the DAQ card that you want to use as the master timing source to the system definition before adding the Slow Background Conversion DAQ card. If both cads are already in the system definition, remove and re-add the Slow Background Conversion-enabled card.

Reported Version: 2013 SP1    Resolved Version: N/A    Added: 06/14/2017
Using the API
522678

Return
Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
When using the System Definition API to programmatically add an FPGA target to a System Definition file, the Parameters section typically included with PWM channels is excluded.

Workaround: Add the FPGA manually to the System Definition via the System Explorer.

Reported Version: 2014    Resolved Version: N/A    Added: 08/13/2015
527148

Return
Programmatic deployment of VeriStand Projects to password protected targets requires user interaction
When deploying a VeriStand Project to a real-time target protected with a password a user is required to interact with a login dialog box. Consequently, programmatic deployment using the API still requires user interaction, preventing truly headless deployment.

Workaround: Have an operator interact with the dialog box or do not use password protected targets for programmatic deployments.

Reported Version: 2014    Resolved Version: N/A    Added: 08/13/2015

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