The NI LabVIEW High-Performance FPGA Developer's Guide

Publish Date: Aug 28, 2019 | 17 Ratings | 4.18 out of 5 | Print

Overview

The LabVIEW High-Performance FPGA developer's guide summarizes the most effective techniques for optimizing throughput, latency, and FPGA resources when using the LabVIEW FPGA Module and NI FPGA hardware.

The PDF version of the guide is available here.


Table of Contents

Introduction 

  • Intended Audience
  • Prerequisites and References

High-Performance FPGA-Based Design

  • Advantages of FPGAs
  • High-Performance LabVIEW FPGA
  • Understanding the NI RIO Hardware Platform
  • NI RIO for PXI and the PC
  • NI RIO for Compact Embedded Applications
  • Selecting an FPGA Platform

High-Performance Programming With the Single-Cycle Timed Loop

  • The SCTL Versus Standard LabVIEW FPGA Code
  • Understanding the SCTL
  • Benefits of the SCTL
  • Restrictions of the SCTL

Throughput Optimization Techniques

  • Increasing the Clock Rate
  • Increasing the Number of Samples Processed per Call
  • Critical Path Reduction
  • Decreasing the Initiation Interval

Integrating High-Throughput IP

  • Recommended Sources of LabVIEW FPGA IP
  • LabVIEW FPGA High Throughput Function Palettes
  • IP Handshaking Protocols
  • Determining Processing Chain Throughput
  • The DSP48 Node
  • The Fast Fourier Transform
  • The Xilinx CORE Generator IP System
  • Integrating HDL IP
  • Integrating IP Into Software-Designed Instruments
  • Integrating IP From the Community

Timing Optimization Techniques

  • Determining and Specifying Latency With the SCTL
  • Reducing Latency Through Parallelization
  • Removing Pipelining Registers
  • Optimizing Data Types

Resource Optimization Techniques

  • FPGA Resource Types
  • Filling Up the FPGA
  • Optimizing Resources Through Data Types
  • Minimizing Front-Panel Controls and Indicators
  • Tweaking Output Overflow and Rounding Options
  • Initializing Feedback Nodes
  • Resource Balancing
  • Multiplexing Logic
  • Using the SCTL as a Way to Save Resources

Data Transfer Mechanisms

  • Throughput and Latency of Data Transfer Mechanisms
  • Transferring Data Within the FPGA
  • Transferring Data between the FPGA and the Host System
  • Transferring Data between Devices

Next Steps

  • Formal Training
  • Evaluating the NI RIO Platform
  • NI Alliance Partners and Services

 

 

 

 

 

 

Back to Top

Bookmark & Share


Downloads


Ratings

Rate this document

Answered Your Question?
Yes No

Submit