The NI Vector Signal Transceiver Hardware Architecture

Publish Date: Mar 27, 2014 | 14 Ratings | 4.64 out of 5 | Print

Overview

With the introduction of the NI vector signal transceiver (VST), National Instruments redefines instrumentation by bringing the flexibility of user-programmable FPGAs to RF instrumentation.

Table of Contents

  1. High-Performance and Revolutionary Design
  2. FPGA Basecard Architecture
  3. Receiver Architecture
  4. Transmitter Architecture
  5. Synthesizer Local Oscillator (LO) Architecture
  6. Calibration
  7. Next Steps

1. High-Performance and Revolutionary Design

The NI Vector Signal Transceiver (VST) family combines RF I/O functionality found in traditional box style vector signal analyzers (VSAs) and vector signal generators (VSGs) along with user-defined functionality to implement signal processing and control all inside a field-programmable gate array (FPGA). The RF input and RF output both have independent local oscillators (LOs), frequency coverage from 65 MHz to 6 GHz, and instantaneous bandwidth of up to 200 MHz. The VST is a single 3 or 4 slot PXI Express module (see Figure 1 below). Multiple Input, Multiple Output (MIMO) configurations can also be created by using several VST modules in a single PXI Express chassis.

Figure 1: NI PXIe-5644R/45R/46R Hardware Front Panel

What’s so compelling about the NI PXIe VST family? The high performance that is achievable in such a small footprint. Through advanced calibration and wideband digital correction, NI’s VST line achieves the performance expectations of R&D-grade instrumentation while maintaining an incredibly small form factor. Coupling compact instrumentation with faster test times and flexibility from the user-programmable FPGA makes the VST ideally suited for RF characterization, verification, validation, and production test.

While high functionality in a small footprint is impressive, the most revolutionary feature of the VST family is the user-programmable FPGA. The Xilinx Virtex-6 FPGA, which is programmable with the NI LabVIEW FPGA Module, is connected to the VSA and VSG baseband I/Q data, as well as 24 digital I/O lines with a data rate of up to 250 Mbit/s. This powerful combination of RF, high-speed digital I/O, and FPGA technologies gives the VST the ability to address a wide variety of applications such as real-time device under test (DUT) control, custom triggering, power-level servoing, software defined radio, channel emulation, and many others.

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2. FPGA Basecard Architecture

The VST family FPGA basecard consists of a Xilinx Virtex-6 FPGA, baseband clocking circuitry, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), a programmable function digital I/O line (PFI 0), digital I/O connector, PCI Express interface, PXI triggers, DRAM, and SRAM.

Figure 2: Block Diagram of the VST Basecard

Xilinx Virtex-6 FPGA

The NI PXIe-5644R/45R contains a Xilinx Virtex-6 LX195T FPGA and the NI PXIe-5646R utilizes the Xilinx Virtex-6 LX240T. The Xilinx Virtex-6 FPGAs are used for system configuration, digital data movement, and digital signal processing. The onboard FPGA has direct connections to the ADCs, DACs, PCI Express bus, DRAM, SRAM, PFI 0, digital I/O, and PXI triggers, allowing for custom programming to meet the needs of many types of applications.

Reconfigurable FPGA Resources

The Xilinx Virtex-6 LX195T and the LX240T FPGAs have the following resources.

Programmable Using LabVIEW FPGA

Experienced and inexperienced users in traditional FPGA design can productively apply the power of reconfigurable hardware through use of the LabVIEW FPGA Module. The LabVIEW development environment, built on the paradigm of data flow and parallelism, is well suited to complement the inherent concurrency of reconfigurable hardware design. The LabVIEW FPGA Module provides users the ability to fully program the Xilinx FPGA present in the VST family.

National Instruments provides LabVIEW sample projects using the Instrument Design Library (IDL) API for the VST allowing users to start utilizing their hardware for test and development immediately. The IDL VIs provide the user access to modify LabVIEW code at both the FPGA and processor levels. Example IDL VIs are categorized according to function, such as configuration, acquisition, generation, digital signal processing (DSP), and synchronization (see Figure 3 below). To learn more about the software of the VST, read the VST Software Architecture white paper or watch the VST webcast.

Figure 3: LabVIEW Sample Project and Instrument Design VI Mapping to VST Hardware

Baseband Clocking

The VST has multiple clocks inside the onboard FPGA. The main clock is the sample clock, used to clock the ADCs, DACs, and their related FPGA logic.

Sample Clock

The sample clock runs at 120 MHz and 250 MHz for the NI PXIe-5644R/45R and 5646R, respectively, with a fully selectable source. Users can select the onboard Temperature Controlled Oscillator (TCXO), REF IN front panel connector, or PXI_CLK 10 as the reference signal for the Phase Lock Loop (PLL). Although the sample clock frequency is fixed at 120 MHz with the 5644R/45R or 250 MHz with the 5646R, high-resolution I/Q data rates can be achieved using the Fractional Interpolation and Fractional Decimation DSP VIs inside the FPGA.

Figure 4: VST Clocking Architecture

FPGA Clocks

The following table lists the clocks in the FPGA. In addition to these clocks, LabVIEW FPGA allows for derived clocks at user-defined frequencies.

ADCs and DACs

The VST uses dual-channel, 16-bit ADCs and DACs while the NI PXIe-5646R makes use of 14-bit ADCs and 16-bit DACs to achieve faster data rates. The ADCs and DACs are clocked at 120 MS/s to provide 80 MHz of complex bandwidth for the 5644R/45R and 250 MS/s to provide 200 MHz of complex bandwidth for the 5646R. All VST ADCs and DACs are automatically synchronized to the sample clock domain inside the FPGA, which enables deterministic latency between receive and transmit. The RF IN and RF OUT IQ data streams are conveniently in the same FPGA clock domain making programming easier permitting synchronization and deterministic latency for real-time test and embedded applications.

PFI 0

PFI 0 is a 3.3 v LVTTL, bidirectional, general-purpose digital I/O signal. The most common use of PFI 0 is as a trigger input or a marker/event output. However, because the PFI 0 I/O buffer is connected directly to the FPGA, its functionality can be programmed for custom applications using LabVIEW FPGA.

Digital I/O

The digital I/O on the VST is accessible via a VHCDI port. There are 24 bidirectional LVTTL digital I/O lines, configurable per port, with four lines per port (six ports total). The digital I/O connector contains the Clock In and Clock Out lines, as well as PFI 1 and PFI 2 lines that can be used for triggering or additional bidirectional digital I/O. The digital I/O buffers are connected directly to the FPGA, allowing the functionality of the individual digital I/O signals to be programmed for custom applications using LabVIEW FPGA.

Cables and Accessories

National Instruments offers several cables and accessories that are compatible with the digital I/O connector. Note that these cables and accessories use a custom pinout that matches the VST digital I/O and maintain the 50 ohm transmission line environment. The use of other VHDCI cables is not recommended.

DRAM and SRAM

The NI PXIe-5644R/45R has two banks of DRAM with 256 MB per bank and a theoretical maximum data rate of 2.1 GB/s per bank; each bank is independently accessible from the FPGA. These DRAM banks are general purpose, but are often used for storing waveforms to be generated or waveforms that have been acquired. 

The NI PXIe-5646R has two banks of DRAM with 512 MB per bank for a total of 1 GB and a theoretical maximum data rate of 2.1 GB/s per bank. The banks are addressable as 512 MB blocks using the NI-RFSA and NI-RFSG driver sets, where each 512 MB block is reserved for Tx and Rx tasks. The Instrument Design Library driver set provides the additional functionality of addressing the total DRAM as 1GB to be utilized by a single Tx or Rx task.

Every member in the VST family has 2 MB of onboard SRAM with a maximum read data rate of 40 MB/s and write data rate of 36 MB/s. SRAM is general purpose memory, which is often used for storing multiple hardware configurations that can be applied directly from the FPGA without intervention from the host.

PCI Express Interface

The VST has a PCI Express, Gen 1 x4 backplane connection, which is used for DMA transfers, programmed I/O, and peer-to-peer streaming.

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3. Receiver Architecture

The VST family features a homodyne RF receiver, also known as a synchrodyne, zero-IF (ZIF), or direct-down conversion receiver. In a homodyne receiver, the incoming RF signal is fed into a frequency mixer just like in a traditional heterodyne receiver. However unlike a heterodyne receiver, the frequency of the LO in a homodyne receiver is identical to, or very close to, the frequency of the incoming RF signal, resulting in a DC-centered or low IF signal such as 10 or 20 MHz.

The input signal is mixed down to baseband and split into in-phase (I) and quadrature-phase (Q) components, where the carrier is in-phase and offset by 90 degrees respectively. The I and Q path signals are then separately digitized resulting in I and Q data. Finally, the I and Q data streams are combined in software, rendering the original signal. Figure 5 shows a simplified block diagram of a homodyne, or zero-IF architecture.

Figure 5: Homodyne (Zero-IF) Architecture Basic Block Diagram

Homodyne (Zero-IF) Receiver Advantages

The homodyne architecture boasts a number of advantages over the traditional heterodyne architecture including simpler design, lower cost, less power consumption, and high selectivity, which allows separation of adjacent channels whose signals overlap. Other advantages include higher potential bandwidths, simpler designs with single LOs, and a smaller footprint due to a more compact design. These advantages are described in more detail below.

1.  Bandwidth. Receivers with single ADCs have a practical upper limit for signal bandwidth of 40 percent of the sample clock frequency. With the same sample clock frequency, homodyne architectures allow double the bandwidth, or 80 percent of the sample clock frequency, because two ADCs are used. In general, ADCs with lower allowable sample clock frequencies have better spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) performance. Homodyne receivers allow wider bandwidths without the trade-off in ADC performance that is a necessary trade-off of single ADC receivers.

2.  Single LO. With multichannel measurement systems becoming more important for multiple input, multiple output (MIMO) applications, sharing the LO is a requirement. With only one LO to share in a homodyne architecture as opposed to multiple LOs in a traditional heterodyne architecture, homodyne architectures become a more cost-effective and less complicated system to configure.

3.  Compact Design. Homodyne architectures have much simpler RF designs over heterodyne architectures. Fewer LO signals; no bulky, expensive RF and IF filters; and fewer conversion stages for the homodyne architecture make for a more compact design.

Homodyne (Zero-IF) Receiver Challenges

Although the advantages are numerous, the homodyne architecture does come with its own set of challenges, such as the inability to implement envelope detection. The VST overcomes this problem by using quadrature detection and digital signal processing.

DC offsets are another challenge of a zero-IF architecture. Any signal that mixes down to 0 Hz in the ZIF structure causes a spectral component at DC. This distortion falls at the center of the instantaneous bandwidth of the data acquisition. A spectrum composed of pasted together data acquisitions, each offset in frequency by the instantaneous bandwidth, will show this DC offset term replicated in the center of each data acquisition. Nulling of the DC offset is accomplished on the digitized I and Q data streams by applying offsets. A separate nulling procedure must be applied for each LO frequency, which is done automatically by running the VST self-calibration procedure.

Receiver Signal Path

The high-level architecture of the VST receiver design is shown in Figure 6. This diagram highlights the calibration synthesizer, optional attenuators for high power, optional amplifiers for low power signals, out of band select filters, additional gain and attenuation signal conditioning, and demodulation over one of three mixers depending on frequency.

Figure 6: VST Receiver Block Diagram

The select filter bank has eight different paths with lowpass or bandpass filters. These filters remove much of the unwanted noise, focusing only on the signal range of interest. After implementing the selectable filter and applying some additional signal conditioning, the RF signal is then sent to one of three demodulators, depending on the signal’s frequency. Each demodulator operates within a specific frequency band to optimize gain and phase signal integrity.

The receiver path includes several solid state attenuators that provide more than 80 dB of attenuation, variable in 1 dB steps. The RF input is AC-coupled. There are three switchable gain amplifiers and a preamplifier to extend dynamic range and improve the system’s noise figure.

A low phase noise LO is supplied internally to connect multiple downconverters with a single LO source. Using the same LO source is useful for phase-coherent signal acquisition applications, such as multiple input, multiple output (MIMO) systems. Using this configuration ensures every RF channel, sharing the common LO, is tuned to the same RF frequency.

The downconverted baseband signal is directly transmitted to the internal ADC channels of the VST. The ADC channels digitize the baseband analog signal and route the result to the onboard FPGA for further processing, and then transfer to the host. The NI PXIe-5644R/45R and 5646R ADCs digitize the baseband analog signal at 120 MS/s over a 16-bit dynamic range and 250 MS/s over a 14-bit dynamic range respectively. 

Downconverter

The VST receiver features a single-stage, direct conversion (I/Q) downconverter. The RF signal is downconverted from the configured LO frequency to DC, where the baseband signal can be digitized for processing. This architecture allows for wide instantaneous bandwidth with high image suppression and minimal LO leakage. Image suppression and LO leakage performance is achieved by wideband quadrature correction. The receiver path is optimized to be used as a vector signal analyzer for wideband demodulation.

Low IF Mode and In-Band Retuning

A low IF receiver is another type of receiver that uses an IQ demodulator, where the block diagram is identical to the zero-IF receiver shown in Figure 5. Unlike in the zero-IF receiver where the LO frequency is positioned to be within the frequency range of the modulated signal, in the low IF receiver the LO frequency is placed outside of the modulated signal range. The result is that the DC component is no longer within the downconverted span. Many of the impairments associated with the DC term such as DC offset, 1/f noise, and in some cases baseband harmonics are no longer an issue.

Any user can combine the capabilities of LO tuning and digital frequency shifting to operate the VST in low IF mode. Acquiring or generating the signal of interest at a digitally shifted frequency from the carrier avoids the implications of LO leakage present in direct conversion topology. The trade-off is the maximum BW of the low IF receiver is half that of the zero-IF receiver given identical ADC sample rates. The NI PXIe-5644R/45R supports up to 80 MHz of complex instantaneous bandwidth while the NI PXIe-5646R provides up to 200 MHz of complex instantaneous bandwidth, both with an additional 4 MHz of complex bandwidth allocated for digital frequency shifting. Additional frequency shift reduces the usable bandwidth to (BW/2) - (x- 2) MHz, where x is the requested digital frequency shift.

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4. Transmitter Architecture

The RF transmitter architecture on the NI PXIe-5644R/45R/46R VST features two modulators, a filter bank, and additional signal conditioning. A high-level diagram is shown in Figure 7.

Figure 7: NI PXIe-5644R/45R/46R Transmitter Block Diagram

Transmitter Signal Path

The two modulators on the VST are optimized for phase and gain balance depending on frequency. The RF transmitter filter bank is the same one that is used in the RF receiver, featuring the same eight paths with lowpass or bandpass filters, as shown in Figure 7.

After filtering, the RF signal then enters the cascade signal conditioning stage, which comprises three programmable attenuators, one selectable amplifier, and two fixed amplifiers. Finally, the RF signal is switched to either the RF Out or Cal Out front panel connectors, depending on whether the transmit path is being calibrated, as shown in Figure 7.

Upconverter

The NI VST RF transmitter path features a single-stage, direct conversion (I/Q) upconverter, which upconverts the baseband signal from DC to RF at the configured LO frequency. This architecture allows for wide instantaneous bandwidth, high image suppression, and minimal LO leakage. Image suppression and LO leakage performance is achieved by wideband quadrature correction. This path is optimized to be used as a CW generator or a VSG for wideband modulation.

The transmitter path includes four solid-state attenuators with more than 100 dB of attenuation, variable in 1 dB steps. An additional switchable gain amplifier is used when generating high-power signals.

A low-phase noise LO is supplied internally on the transmitter path, which is used to connect multiple upconverters with a single LO source. Using the same LO source is useful for phase-coherent signal generation applications, such as MIMO systems. When using this configuration, every RF channel sharing the common LO is tuned to the same RF frequency.

Considering Average Power and Crest Factor

Crest factor is the ratio of the peak signal power and average root-mean-square (RMS) power. The crest factor for a sinusoid signal, as is used in CW mode, is 3 dB. In other words, the average RMS power of the sinusoid is 3 dB less than its peak power. For modulated signals, specifically OFDM, the crest factor can be much larger, in the order of 10 dB to 12 dB.

It is important to consider both the average RMS power and the crest factor of a signal when configuring the device for generation. The NI PXIe-5644R/45R/46R supports a maximum average power output power of 6 dBm, with support for up to a 12 dB crest factor. Beyond 6 dBm average power, the device is not guaranteed to perform linearly. More importantly, if the average power is set to be higher power than 6 dBm and the crest factor of the signal is still 12 dB or more, severe saturation might occur or the reverse power protection circuitry of the VST may be enabled.

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5. Synthesizer Local Oscillator (LO) Architecture

The NI PXIe-5644R/54R/46R features a frequency range of 65 MHz to 6 GHz with less than 1 Hz of tuning resolution, combining LO step size capability and frequency shift via DSP implemented on the FPGA.

There are two LO stepping modes:

  1. Integer stepping mode with 4, 12, and 24 MHz steps
  2. Fractional stepping mode with 200 KHz steps. This mode has more granularities but also has more spurs. This is the mode where specifications are guaranteed.

The VST synthesizer LO is part of a phase lock loop (PLL) using a 120 MHz or 250 MHz clock reference clock for the PXIe-5644R/45R or PXIe-5646R, respectively. The PLL contains three voltage-controlled oscillators (VCOs) at frequencies 2 to 2.5 GHz, 2.5 to 3 GHz, and 3 to 4 GHz. If the desired output signal is less than 2 GHz, the signal is switched into a divider. Likewise, if the desired end signal is 4 to 6 GHz, then the signal is switched into a doubler (x2 multiplier). This stage is followed by a filter bank with additional dividers to remove harmonics content and then split to be routed to the RF mixer and the LO Out port for use in MIMO applications, if selected. To increase the performance of MIMO configurations, there is also a calibration ADC available to calibrate the LO path before it is exported. 

Figure 8: NI PXIe-5644R/45R/46R Synthesizer LO High-Level Block Diagram

Spectral Purity

When the incoming RF signal mixes with the LO, it inherits the spectral skirt of the LO. For this reason, it is very important for the LO to have very good spectral purity. Frequency-banded VSAs typically use off-the-shelf integrated synthesizers, which typically do not perform as well as a traditional discrete synthesizer. The VST is designed to be a wideband instrument. As such, it features a traditional discrete synthesizer architected specifically for this application. This enables excellent measurement performance across the entire frequency range of the instrument.

The NI VST has three different PLL bandwidth options, outlined below. The trade-off of these options is phase noise versus settling time.

  1. High bandwidth—Lower frequency settling time (250 us), higher phase noise
  2. Medium bandwidth—Moderate settling time (500 us), excellent phase noise comparable to the low bandwidth option, which is optimized for narrow frequency bands (500 MHz or less)
  3. Low bandwidth—Optimized phase noise, higher frequency settling time (1 ms)

When measuring RF standards such as 802.11ac and LTE, the medium bandwidth option is typically recommended, but the low bandwidth option can also be used if tuning speed is not important. Fast frequency hopping is an example of when the high bandwidth option would be used. Figure 9 shows the difference in phase noise depending on which of these PLL bandwidth options are selected. Figure 10 below shows the phase noise at different frequencies using the medium bandwidth option only.

Figure 9: NI PXIe-5644R/45R Measured Phase Noise at 2.4 GHz Versus Loop Bandwidth

Figure 10: NI PXIe-5646R Measured Phase Noise at 2.4 GHz Versus Loop Bandwidth

Figure 11: NI PXIe-5644R/45R Measured Phase Noise at 1 GHz, 2.4 GHz, and 5.8 GHz With the Medium PLL Bandwidth Option

Figure 12: NI PXIe-5646R Measured Phase Noise at 1 GHz, 2.4 GHz, and 5.8 GHz With the Medium PLL Bandwidth Option

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6. Calibration

Every NI VST is individually calibrated for accurate frequency and amplitude response at the factory. Each ships with a calibration certificate verifying NIST-traceable accuracy levels. External factory calibration adjusts the frequency reference, internal LO path gain, external LO path gain, RF input gain, and RF output gain. For the NI PXIe-5644R/45R/46R to continuously meet specifications, a one-year (or two-year with relaxed specifications) factory calibration is recommended.

Calibration Path

The NI VST relies on a fixed path between the RF input and RF output calibration sections of the device. This path is provided by the SMA-SMA semirigid cable connecting between the CAL IN and CAL OUT front panel connectors. This cable should never be loosened or removed from the front panel of the device, as it prevents proper self-calibration functionality.

Self-Calibration

In addition, self-calibrations are recommended whenever there is a change in the environment’s temperature by more than five degrees Celsius (5° C). Temperature drift can lead to performance degradation of several specifications. Perform self-calibration to compensate and optimize the performance for a given ambient temperature. Self-calibration adjusts the following parameters to facilitate temperature correction:

    1. LO path gain
    2. RF input gain
    3. RF output gain
    4. RF input LO leakage
    5. RF output LO leakage
    6. RF input image suppression
    7. RF output image suppression

The calibration synthesizer provides a stable frequency pared with a low distortion amplifier to provide stable amplitude. The calibration table on the device sweeps both frequency and power. The NI VST also takes advantage of an advanced calibration technique, vector calibration over frequency, which allows the NI VST family to achieve R&D grade performance in a compact form factor.

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7. Next Steps

Watch the webcast 

See the product details 

Download the ekit

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