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voltage_input_test.vi
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This document will discuss the technical details of testing the voltage input thresholds on semiconductor devices using a test system created with the PXI platform. To learn more about the hardware components of this test system, click here. To learn more about the software components of this test system, click here. To return to the DC Parametric Validation Reference Architecture main page, click here.
Voltage Input Thresholds are essential parameters that describe how a digital pin recognizes the outside world. Tests for voltage input thresholds can be used to make important distinctions about the characteristics of a device during validation, as well as the quality of a device during production test. These tests can be conducted on a wide range of devices from semiconductor chips to fully integrated consumer electronics devices. This paper will describe, in detail, the process of testing the voltage input thresholds on a packaged semiconductor chip.
The essential connections for performing voltage input tests using this PXI system are as follows: there must be a connection from the utility channel on the PXI-4130 Power SMU to the VDD and VSS terminals of the chip in order to provide power, and there must be a connection from the SMU channel of the PXI-4130 to the pin under test in order to source the voltage seen by the DUT. Additionally, there must be feedback from the device under test as to what logic state is currently detected on a particular pin - this is typically achieved through a single or multiple feedback lines to a digital I/O instrument. This requires that the DUT has been conditioned into a state to where it can provide such feedback. One such state which is typically used performs a logical "OR" of all of the digital inputs on the pin, passing the status to a single digital output pin. In that manner, any input pin that is provided a logic-high value will result in the single output going high, and therefore is easily detectable.
Figure 2: Testing for Power Consumption
By measuring the current draw from the VDD terminal of the device (the IDD), we can calculate the power consumption as:
P = VDD * IDD
If the power measured is higher than expected, it is indicative of a short-circuit or resistive fault in the internal circuitry of the chip. On the other hand, if the power consumption is lower than expected, it is indicative of a non-functional chip. The limits for these tests are highly dependent on the state that the device is set to.
Power consumption tests are essential for establishing the proper operation of a chip in a variety of states including:
• After being reset, which checks for Gross IDD, the first test to verify overall functionality.
• In Standby Mode, which checks for Static IDD in order to characterize power consumption when off, or inactive. Currents can be in the uA level and below for this test.
• In multiple quiescent logic states, which checks for IDDQ – a more rigorous test of the low-power performance of a chip. Again, currents can be in the uA level and below.
• While Active, which checks for Dynamic IDD, the operating power.
If the device is drawing too much power in any of these states, that’s a big clue that there’s a structural issue inside the chip, and that it should not be used in a final environment as it has the potential to damage other components. As can be seen from this set of tests, the SMU in this scenario must act as a constant voltage source while measuring the current draw, which can be down to nA-level for static and IDDQ tests and up to 1 amp and higher for dynamic tests. Here, the flexibility and precision of the PXI-4130 SMU are important benefits.
Step 1: Power the DUT by applying VDD
To power the DUT, the PXI-4130 SMU should be set to output the rated voltage of the device (usually 3.3V). In addition to this voltage setpoint, it also very important to set a current limit to ensure that the DUT does not draw excessive currents if it is faulty or shorted.
Step 2: Condition the DUT into the appropriate state
Because the power draw can be affected by the state of a device, it is essential that the device is preconditioned to a known state prior to the power being measured. This preconditioning is performed by using the PXI digital I/O device to generate the appropriate pattern to put the DUT into the desired state.
In the case of a Gross IDD test, a conditioning pattern is not necessarily needed. To save time, power can be tested immediately after voltage is applied to the DUT in order to get a general idea of the device's consumption. In other cases, a reset pattern can be used.
Depending on the device, Dynamic IDD tests can require continuous patterns to be applied in order to keep the device active through constant stimulation. In this case, the power must be measured while the conditioning pattern is being applied.
In the case of an IDDQ test, multiple conditioning patterns can be applied sequentially and power is measured after each step. These patterns are designed to keep the device in a low-power or quiescent state while still activating and changing internal logic sections.
Step 3: Measure the Current
The next step is to measure the current draw of the VDD terminal using the SMU. It is important to consider the range and the resolution needed on the expected current measurement. For instance, a static IDD measurement can result in currents at or below 1uA, so it is important to use the SMU's lower ranges to achieve the necessary precision. In this case, the PXI-4130 can be set to its lowest range of 200uA in order to achieve 1nA current measurement resolution. Some devices may also have an associated settling time before the current draw stabilizes, so a delay can also be necessary prior to measuring.
Step 4: Calculate Power and compare
The final step is to convert the measured current into an associated power draw and compare that to the acceptable limit for a functional device. These limits are be both device dependent and state dependent.
The software for this Input Voltage Threshold test is developed using NI LabVIEW and NI Switch Executive. LabVIEW is used as the primary Application Development Environment (ADE) while Switch Executive is used to configure routes on the high-density matrix. For simplicity, this code only tests for the Voltage Input High (VIH) threshold. To add in a test for VIL, repeat the same steps, but sweep the SMU down from a high voltage to a low voltage and watch for the digital transition from high to low.
The following software versions were used to implement the Input Voltage Threshold Test:
LabVIEW 8.5 Graphical Programming Environment
Switch Executive 2.1.1 Switch Management Software
The LabVIEW code described in this document can be downloaded from the link at the top of this document.
Note: Functional blocks in the LabVIEW graphical programming language are known as ‘Virtual Instruments’ or ‘VIs’. The acronym ‘VI’ will therefore be used when describing procedures in this section.
The software steps to test the voltage input thresholds are as follows:
Step 1: Initialize the PXI-4130 based on the resource name, then set the utility channel to power your device by changing the voltage set point to the desired VDD. Also remember to set the current limit to the max allowable current in order to protect your device and test setup. Once all settings are configured, enable the output of the utility channel in order to provide power to the device under test.
Step 2: If necessary, add the digital I/O code here to condition your DUT to the appropriate logic state such that there is feedback of what a particular pin sees as a logic high. One example of this would be to make a single output pin be the logical OR of all input pins.
Step 3: Set the SMU channel on the PXI-4130 to begin at 0V and have a current limit 200uA for the subsequent tests. The voltage will be changed programmatically later.
Step 4: Initialize a session to the matrix switch via NI Switch Executive. The NI Switch Executive (NISE) Virtual Device Name is input to the Open Session VI to begin communication with all the switches in the system. The individual routes to each pin on the device under test are retrieved from the route group specified, and used later to make the connections. To download the "extract_routes" subVI and an example NI Switch Executive configuration, return to the software components section of this reference architecture.
Step 5: Connect the SMU to the pin under test and ground all other input pins using the appropriate switch routes. Next, configure the SMU to conduct a voltage sweep from 0 to 3 V. At each point in the sweep, test to see if the DUT has recognized a logic-high on the input. Continue until the DUT sees a logic-high value, or until the upper limit of the sweep has been reached.
Step 6: Measure the voltage value on the specified output channel of the SMU at the time that the DUT recognizes the logic-high. Alternatively, the last setpoint of the sweep can be used instead of teh measured value. Next, analyze the data to determine whether the pin passed or failed the Voltage Input Threshold test. If the voltage threshold is too high, that means that the chip requires a voltage too close to VDD in order to function, and is therefore faulty.
Step 7: Disconnect the switch channels that connect the SMU to the pin under test
Step 8: Show a histogram of the pin measurements and display the individual values in a table.
Step 9: Power down and close SMU session.
Step 10: Disconnect all switch channels and close switch session.
The front panel of the attached example code allows the user to control the settings of the SMU, Switch, and HSDIO instrument. It also presents test results for the Input Voltage Threshold test in a table and a histogram.
