This document discusses the details of Bit Error Rate Testing (BERT) testing using National Instruments hardware and software. To learn more about the hardware components of this test system, click here. To learn more about the software components of this test system, click here. To return to the DC Parametric Testing Reference Architecture main page, click here.
Testing for BERT requires a bit generator or a test pattern generator, and a receiver, which is used to compare that pattern. The pattern generator sends a bit stream (stimulus) to the device under test (DUT) which then responds back with another bit stream. The receiver compares the actual response from the DUT with the expected response which is provided by the user. The calculated result is the ratio of errored bits to the total number of transmitted bits usually shown in an exponential form, such as 2^B, where B is the BER ratio. This is done for the large number of errors that occur.
2. Hardware Setup
This reference architecture uses the NI PXI-6552 to conduct the BERT test. The hardware-compare feature on the NI PXI-6552 is uniquely suited for BERT testing as it provides the ability to perform digital comparisons of data on device itself. This allows for real time hardware comparison, which is not possible if data is transferred back to the host computer.
An example of a semiconductor device for which a BERT test would be useful is a deserializer or SerDes. Deserializers take in serial digital data and output parallel data based on the serial input. A use case of a deserializer would be for acquiring signals of speeds higher than the capabilities of existing hardware. The deserializer takes in fast serial data and outputs slower parallel data, thus making it easier to acquire the parallel data (on a higher number of channels).
To set up the hardware for testing the DUT, configure one of the 32 bidirectional pins on the NI PXI-6552 high-speed digital board as an output. Based on the number of lines in the parallel response data, the input pins on the NI PXI-6552 are set up for acquisition.
Figure 2 – Hardware Set up
The stimulus data that can be seen in the diagram above can be created programmatically in a language such as NI LabVIEW, or an easy to use interface such as the NI Digital Waveform Editor (DWE). The DWE offers a configurable software environment for creating digital vectors. The above methods can also be used for creating the expected data. The acquired data is compared to the expected data to check for errors.
As seen in the image below, the stimulus data is loaded onto the onboard memory to be generated. The stimulus data causes the DUT to respond with data (parallel data in the case of a deserializer). The Expected Data is also loaded into the on board FIFO, which will later be compared (on the FPGA, real time) to the data that is read in.
Figure 3: Hardware Compare on the NI-655X devices
For most digital tests performed on semiconductors, synchronization is a requirement, whether it is between the board and the DUT or even between generation and acquisition sessions. For this BERT test, it is important to synchronize the generation and acquisition sessions because hardware compare is used to check for bit errors that occur on the expected data.
Some external connections need to be made to synchronize the generation and acquisition sessions. The diagram below shows the external connections that are required. The software steps are discussed in detail later.
Figure 4: External connections on the NI PXI-6552 for synchronization
To perform the test, the stimulus data (loaded on the on-board memory), is generated, and the expected data is stored in the FIFO. The deserializer accepts the serial stimulus data and outputs the expected data. The parallel data is then read in on the input pins on the NI PXI-6552 and compared with the expected data stored on the FIFO.
Using the NI-HSDIO driver, data such as the error locations, number of errors, and total samples compared can be read back from the on board FPGA. The bit error rate is calculated by dividing the total number of samples by the number of sample errors that occurred.
4. Software Setup
The software used in this system is architected using NI LabVIEW and the NI Digital Waveform Editor. Using the NI-HSDIO driver API for LabVIEW, the high speed digital board can be programmed to utilize the hardware-compare feature for BERT. The hardware compare feature enables the device to utilize the on board FPGA for comparison of data. In this example system, the NI-HSDIO driver is used to program the FPGA for hardware-compare.
First, the Digital Waveform Editor (DWE) must be used to create the stimulus data. Then the appropriate Hierarchical Waveform Storage (HWS) file containing the stimulus data is chosen on the front panel of the attached LabVIEW virtual instrument (VI). Results of the BER reading are displayed on the graph on the front-panel.
Figure 5: Front Panel of Hardware Compare BERT VI
NOTE: By default the attached LabVIEW VI is set to run as a loop back test. The test can be modified for different types of device under tests (DUTs). As an example, for a deserializer only one channel would be used for outputting the serial data. On the high speed digital board, channel '0' can be configured for output. Based on the number of parallel channels that the deserializer outputs on, input channels will be configured appropriately on the high speed digital board.
Step 1: To conduct the BERT test the acquisition and generation sessions on the digital board must be synchronized. On the generation side the sample clock must be exported to the ClkOut pin on the Digital Data and Control Connector (DDC) by connecting the ClkOut pin on the Digital Data and Control Connector (DDC) to the Strobe line.
For the acquisition session, the sample clock should be set up to use the strobe line as its reference clock.
Step 2: A trigger will have to be shared between the generation and acquisition sessions for complete synchronization. An external connection also needs to be made between the lines PFI1 and PFI2 on the DDC. On the generation session, the data active event is exported to the PFI 1 line, using the NI HSDIO Export Signal.
Step 3: The trigger is accepted in the acquisition session by using the PFI 2 line for triggering the start trigger.
Step 4: To set up hardware compare on the digital board, property nodes are used for both the acquisition and generation sessions. Property nodes provide access to driver level components which might not be accessible from subVIs. The Hardware Compare Mode is set to "Stimulus and Expected Response". This sets up the device to compare expected data to actual in real time. If this property is set to "Stimulus and Expected Response" or "Expected Response Only", the generation engine sends the expected data to the FIFO, to be compared with the acquired data.
Step 5: In the acquisition session, the 'Fetch Relative To' property should be set to 'First sample', and also a Reference trigger should be configured, which is never sent to set up a continuous acquisition session.
Step 6: For the generation session the NIHSDIO Configure generation repeat VI is used to continuously generate data.
Step 7: Once the set up is done, the NIHSDIO HWC Fetch Sample Errors can be used to fetch all the errors that occurred.
Step 8: Also, Bit Error Rate (BER) is calculated by dividing the Number of Sample Errors with the Total Number of Samples Compared.
Step 9: The calculation of Distribution of errors is done in software. Using nested for loops, the locations of the errors are checked and stored in the shift registers. This location array is then passed to a General Histrogram.vi subVI which builds the graph to be displayed on the front panel.
National Instruments high speed devices are ideally suited for applications such as BERT. The NI PXI-6552, which is used for this demo, has features such as Hardware Compare, which perform on board comparisons between generated signals and acquired signals. The easy to use NI-HSDIO driver can be used for programming the NI PXI-6552, for generation and acquisition, and the otherwise complex hardware compare feature.
6. Related Links