### 1. Downloads

**LabVIEW 2009 -** This IP set is now in LabVIEW FPGA under the High-Throughput Math Palette

**LabVIEW 8.6 Fixed Point Math Library** - Version 8.6 (4.8 MB) User's Guide (1.1 MB)

**LabVIEW 8.5 Fixed Point Math Library** - Version 8.5 (28.6 MB)

### 2. Included Fixed-Point Math VIs

- Add
- Subtract
- Multiply
- Divide
- Reciprocal
- Square Root
- Sine
- Cosine
- Arctangent2
- Polar To Rectangular
- Rectangular To Polar
- Hyperbolic Sine
- Hyperbolic Cosine
- Exponential
- Natural Logarithm
- AddSub
- Discrete delay
- Integer accumulator
- To Fixed-Point Conversion

### 3. Differences between Fixed-Point Math Library and FPGA palette IP

**Not Always Exactly Like LabVIEW Counterpart** - The main difference between the IP in the FXP Math Library and the FPGA palette IP is that it does not always give the same behavior as the same function in LabVIEW for a PC. Careful consideration is given to the IP in the FPGA palettes to make sure that the experience is unchanged between particular functions on multiple platforms. However, for some corner cases or input parameters, outputs from the Fixed-Point Math Library can be undefined or unexpected. The library IP also does not support the overflow bit handling introduced in LabVIEW 8.6. In some cases, these decisions were made to streamline the IP to use less resources. Nevertheless, it means that more of the burden of complexity and testing is placed on the user. These corner cases are described in the help documentation for the particular function.

**Additional Math Functions** - The Fixed-Point Math Library currently has a number of functions not present in the LabVIEW FPGA palettes today, such as trig, log, and rectangular/polar transformations.

**Single-Cycle Loop Compatibility** - Each of the math library IP blocks can be configured to work in a Single-Cycle Loop. However, you must deal with the boolean handshaking protocol, which adds some complexity in programming. Basically, the functions do not give valid results every iteration of the loop and users must handle this when passing data to the next function. This is very similar to the protocol currently used by windowing and FFT in the single-cycle loop.

**Configurable Pipeline Stages** - Many of the functions have configurable pipeline stage within the IP configuration panel. This allows the IP to meet timing at a higher throughput rates at the expense of adding extra clock cycles to the latency of the system. To learn more about the concept of pipelining refer to the help topic about optimizing for size and speed in the LabVIEW FPGA documentation.

**Labeled Terminals** - One helpful aspect of the Fixed-Point Library is that the inputs and outputs are labeled with the configured bit width. This is nice as your code gets larger to easily see how the bit widths are growing and contracting through your program. Remember you can use Context Help <Ctrl+H> to quickly see the bit width configured for a particular wire when using functions without labels.