Multi-Chassis TClk Synchronization with PXIe-6555/6556

Publish Date: Mar 31, 2014 | 0 Ratings | 0.00 out of 5 | Print | Submit your review


This white paper is a case study that can be helpful for any multi-chassis TClk synchronization between compatible SMC based devices (Digitizers, HSDIO, Function Generators) and using multiple PXI/PXIe chassis. This process can be difficult to begin understanding how this type of synchronization is done successfully. With the help of this white paper, you will be able to understand the key features that makes this synchronization successful. This white paper is not intended to cover all details to synchronization. Please refer to the links at the end of this white paper for more information.

Synchronization is a very common, yet complex application when it involves several devices that do not reside on the same backplane and also require individual synchronization for the most accurate timing possible. In this white paper, we will identify a common use case for HSDIO Multi-chassis Synchronization with PXIe-6555 and PXIe-6556 modules, and we will identify technical caveats that will be important for understanding and making your application successful.

High Level Goals to Synchronization

The goal of board to board synchronization is to send or receive data simultaneously for a particular application. This allows for channel expansion in the system to address DUT's that have a high pin count, or it can address parallel testing on multiple DUTs at the same time. The keys to synchronization board to board are as follows:

  • Having the sample clock on each board phase aligned with one another (reference clock inputs all from a single clock source)
  • Having both boards begin their acquisition/generation at the same time (master trigger to slave via TClk, accounting for various delays in propagation and generation)
  • For HSDIO, aligning the data that is being generated by the generation timing engine and acquired by the acquisition timing engine. (Source synchronous sampling, stimulus/response applications)

Beyond board to board synchronization comes chassis to chassis synchronization. Here, we introduce another set of keys to make synchronization from multiple chassis successful:

  • Sharing the reference clock across both chassis via a Timing and Sync module in the timing slot of each chassis (driving PXI_CLK10 from one chassis to another on both backplanes)
  • Sharing the master trigger from the master chassis to the slave chassis, and choosing the master sessions on each chassis in TClk (exported and imported through T&S board, then routed to the backplane on each chassis)
  • For HSDIO, adjusting Data Active Event via Internal Route Delay and delaying the data to reach the appropriate setup and hold time for the system.

Board and Chassis Connections

Depending on your system, this setup will vary. For the sake of this example, we will imagine two PXI-1075 chassis connected via MXI (daisy chain configuration) with two 6674T modules and several PXIe-6556 boards in each chassis.

It is important to note that whether MXI is used or whether each chassis has its own controller does change the configuration details required for the system to be successful. The case study here assumes that a daisy chain configuration is being used, and that the Master chassis controls the Slave chassis.

CLK IN, CLK OUT, PFI0, and PFI1 will all be connected for the master 6674T. The slave 6674T will have all but CLK OUT, since we will only use one clock source for our reference clock. The PXIe-6556 modules can be connected to their DUT via the D4 VHDCI cable or the Flying Lead cable.  PFI0 on the master PXIe-6556 will be connected to it's respective 6674T for trigger export/import.  The trigger from the master board will be routed to all other boards in their respective chassis through the backplane.

API Implementation

On the side of this white paper is an example VI with the details on how this synchronization was implemented for two 6556 boards in each chassis, one master board and one master chassis, and how signals were routed using the 6674T.

Implementation Details

You cannot use Data Active Internal Route Delay if you are attempting to perform a source synchronous application that requires STROBE to be the input CLK on the acquisition session.   

When using TClk, you only want to TClk generation sessions together on each HSDIO board, then use the exported or delayed Data Active Event to begin acquisition. This will correctly synchronize each board in the system and can be modified to suit a particular DUT. The example uses delayed data active, which is an internal route that does not take into account propagation delay in the system. To adjust for propagation delay, use the Data Active Internal Route Delay control on the front panel of the VI. This adjustment will vary based on cable lengths used in the system and to the DUT, but you have up to 24 samples of delay to adjust for, which should cover most application.

There will be some TClk properties that will need to be modified to make the system work. These properties are Data Position Delay and TClk Master Sample Clock Delay. These properties will allow you to align the setup/hold time window of your sampling based on the various delay in your system. The SyncPulseSrc is used by TClk to align phases of the reference clock each chassis is using, and the board that sets these properties are in the master board session of each chassis. The ExportedSyncPulseOutputTerm ties the master Sync Pulse sender to the backplane trigger line that sends the Sync Pulse to all other boards in the chassis. In this example, PXI_Trig2 and PXI_Trig1 are tied together to represent an exported Sync Pulse that is routed from the master 6556 to the 6674T, then sent back to the backplane on PXI_Trig1 for the other 6556 slaves to receive the Sync Pulse.  This is performed so that the Sync Pulse is aligned when it is sent to the master chassis's backplane, and the slave chassis via PFI1. 

TClk identifies which board is the master session by the StartTrigMasterSession property, which will select the board to be used for the master start trigger on each chassis. This is always the first resource entered in on the example, and can be modified if needed. Otherwise, be sure to always list your master 6556 first in the resource array index labeled HSDIO Resource Names.

Using NI-TClk, there will be some tricks that need to be performed to make sure the system can be fully synchronized. The first T&S board (6674T in this instance) will output its onboard oscillator to ClkOut and that clock is split (via BNC splitter or other means) and fed back into ClkIn on each 6674T so that they can be used to drive the PXI_Clk10_In signal and drive a new PXI_CLK10 reference clock on each backplane of the two chassis. PFI0 will receive the Start Trigger from the master board session. 


This example design is not intended to give the only configuration options for synchronization in a multi-board, multi-chassis system, but to help you understand the components which are commonly used in synchronization. The example VI for this design is attached to the side of this white paper as a reference that you may use in building your own synchronous design. Please leave a comment if you feel there is any missing information, and it will be modified in the future.

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