FPGA Power Measurement and Gain Adjust

Publish Date: Nov 21, 2013 | 1 Ratings | 2.00 out of 5 | Print | Submit your review


The FPGA Power Measurement and Gain Adjust sample project enables hardware-based leveling of RF power amplifier output. This document describes the underlying engineering reasons for this task, lists the contents of the sample project, and specifies where to obtain further documentation.

Table of Contents

  1. Background
  2. Project Contents and Requirements

1. Background

In wireless communication systems, a power amplifier (PA) IC increases signal strength before sending the signal to an antenna. PAs are typically specified to have a specific performance at a given output power level. Therefore, it is important to test PAs while they are operating at the given output power level. 

However, the gain of the PA is typically only roughly known. Additionally, the gain is non-linear over the operating range of the device, meaning that the gain lowers as you approach the maximum output power. For these reasons, you must level the PA output prior to making any performance measurements. The FPGA Power Measurement and Gain Adjust sample project enables you to level PA output. 

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2. Project Contents and Requirements

The sample project consists of LabVIEW FPGA code and LabVIEW host code. The sample project requires the LabVIEW FPGA Module and the LabVIEW Development System.


The sample project contains one top level VI which is used to implement the hardware-based power leveling. The sample project also contains two additional VIs which are used for debugging purposes. 

LabVIEW Host Code

The host code consists of several different VIs which communicate with the FPGA VI. These host VIs are used to configure, initiate, and monitor the autoleveling process. 


Documentation for this sample project is found in the documentation folder contained within the download. For further explanation of the theory of operation of this sample project, as well as an example of using the sample project for power leveling with the NI PXIe-5644R vector signal transceiver, see FPGA Servoing for Power Amplifier Test on the NI PXIe-5644R.

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