FPGA Digital Debounce Filter Reference Example

Publish Date: Apr 19, 2010 | 8 Ratings | 3.75 out of 5 | Print | Submit your review

Overview

This simple example VI shows how to implement a digital debounce filter in LabVIEW FPGA. This code can be used to clean up a digital input signal which may contain extra pulses (bounces) when a relay or switch is closed.

Table of Contents

  1. Theory of Operation
  2. LabVIEW FPGA Implementation

Installation

Download and unzip the ZIP file above to a working directory. The ZIP file contains a LabVIEW project and associated VIs.

1. Theory of Operation

When acquiring digital signals in an industrial or otherwise electromagnetic noisy environment, it is common to see some bounces on the acquired signals whenever the signal changes state. These bounces appear as extra pulses close to the actual transition of a digital signal. When processing digital signals for pulse counts such as a quadrature encoded value, it is desirable to avoid theses bounces or eliminate them before processing the signal. This type of filtering or processing is commonly called debouncing as it removes the bounces from the digital signal.

The following time diagram shows a typical digital signal with some bounces and the corresponding sampled data. The Unfiltered Sampled line shows the data as it it acquired by a digital input channel which samples the signal at a defined sample clock rate. Note that the unfiltered sampled data does not see changes in the signal until the next clock cycle of the sample clock. This means any very short pulses between two clock cycles are not observed at all. Short bounces in the signal that happen to occur across a clock cycle are observed in the sampled data.

Figure 1: Example of a raw signal and the sampled data using a clocked digital input 

A common algorithm for debouncing a digital signal is to process the raw (unfiltered) sampled data and only pass through a change in state whenever the sampled data has remained constant for a defined period of time. Any pulses shorter than the filter time constant are removed and not passed through. The following graph shows the same signal, the raw (unfiltered) sampled data and the debounced (filtered) data using a time constant of two sample clock cycles.  In order to avoid counting extra pulses in our signal the sampled data is filtered by looking for pulses that hold the same state for at least two clock cycles before the change in state is passed to the output. Using the debounce filter extra short pulses (bounces) that are present in the unfiltered sampled data are removed. The red circles in the timeline indicate when the unfiltered data has remained constant for two clock cycles at which point the filtered data state is updated.

Figure 2: Time waveforms of a raw signal, the unfiltered and filtered (debounced) sampled data

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2. LabVIEW FPGA Implementation

Using LabVIEW FPGA it is straightforward to implement such a debouncing algorithm. The algorithm shown in the following diagram compares the new input signal to the current output signal and looks for a change in state. Once the input signal changes state the algorithm starts incrementing a counter from 0 and keeps counting as long as the input remains different from the output. When the counter exceeds the limit (filter time constant - 'Cycles to Filter') it passes the new input value to the output and resets the counter to 0. If the input changes back to the original state before the counter has exceed the time constant, the counter is reset to 0 and the algorithm waits for the input signal to change state again.

Figure 3: LabVIEW FPGA diagram for debouncing a digital signal

The FPGA Debounce Filter VI is set to be reentrant so that it can be used for multiple digital input signals in parallel. Each copy of the VI on the LabVIEW FPGA diagram will generate a separate copy of the algorithm on the FPGA. The attached LabVIEW project includes the FPGA Debounce Filter VI and an example showing how to use this filter.

Figure 4: LabVIEW FPGA example using the Debounce Filter VI on 8 digital input channels

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Attachments:

FPGA Debounce Filter.lvproj

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