Testing Motor Controllers Using FPGA-Based High-Speed Hardware-in-the-Loop Simulators

Publish Date: Jul 05, 2011 | 11 Ratings | 3.73 out of 5 | Print | 9 Customer Reviews | Submit your review

Table of Contents

  1. Introduction
  2. The Need for FPGA-Based Hardware-in-the-Loop Simulators
  3. Design Assumptions
  4. Solution Flowchart
  5. Ways to Tackle Fixed-Point Implementation Challenges
  6. Examples
  7. Conclusion

1. Introduction

Electric motors play an important role in modern life. Because of safety, cost and efficiency considerations, engineers, especially hybrid electric vehicle (HEV) engineers, often like to test real motor controllers against simulated motor models in certain real-time environment.

HEVs attract great attention because of their economical and environmental advantages. Electric motors are the key component of HEVs.  Because of the big size and the high cost of electric motors and power electronic devices in HEVs, hardware-in-the-loop (HIL) testing is greatly desirable. This document talks about designing FPGA-based high-speed HIL simulators for testing motor controllers. The following figure shows an HIL testing system.


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The motor drive simulator includes the DC voltage source, the inverter bridge, and the motor.  We support permanent magnet synchronous motors (PMSM) and brushless DC motors (BLDC).

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2. The Need for FPGA-Based Hardware-in-the-Loop Simulators

Modern motor drive systems are usually driven by pulse width modulation (PWM). The following figure shows the basic concept of PWM.


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The motor controller compares the reference wave with the triangle carrier wave to determine states of gate control signals.

When  , the upper gate signal is true and the lower gate signal  is false

When  , the upper gate signal is false and the lower gate signal is true

Accurately detecting switching moments of gate signals is very important for the simulator to produce correct simulation results.  Otherwise, the simulator might produce inaccurate results like jitters and non-characteristic harmonics, or even become unstable.  The following current waveform shows simulation results of a PMSM motor drive.


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The PWM frequency is 10 kHz. You can see that the 50 kHz simulation loop rate is not fast enough to let the simulator detect switching moments and then produce an accurate result. You can find that the result contains unwanted harmonics and deviates greatly from the expected one.  The result of the 200 kHz loop rate is much better.

So in order to produce accurate results, the sampling interval of the simulator must be much smaller than the PWM period of the controller.  This kind of high loop rate request makes the FPGA-based solution an ideal choice.  Both our fixed-point PMSM model and fixed-point BLDC model take less than 40 cycles to complete one simulation step. They can help you achieve a very fast loop rate on FPGA.

Tip:  Sometimes the expected simulation loop rate is beyond the rate that an analog I/O can achieve. Usually you don’t need to update the analog I/O (torque input, current output, etc) to match the simulation loop rate. You can utilize multirate programming to keep the digital I/O and the simulation loop running at the expected fast rate to detect the switch moments of gate signals accurately and put the analog I/O in another loop. You then use FIFO to transfer data between these loops.

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3. Design Assumptions

a.       Ideal Switch Approach

Each converter leg contains one power electronic device and one anti-parallel diode. The power electronic device can be an IGBT, MOSFET, or GTO. You can model the power electronic device as an ideal switch, which is an ideal short circuit when the status is closed and is an ideal open circuit when the status is open. The gate signal of the power electronic device controls the status of closed or open. You also can model the anti-parallel diode as an ideal switch. The anti-parallel diode works only during the dead time. The direction of the motor current determines the status of closed or open.

The ideal switch approach works well for the system level simulation. In addition, the ideal switch approach can greatly speed up the simulation.

b.      The Integration Method

The mathematical models of motors are sets of differential equations. So when you simulate motor drive systems on FPGA, you are actually integrating differential equations on FPGA. Because the expected loop rate is at the step size of several microseconds, you can choose the simplest integration method, the Euler method, which works well at small step size.

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4. Solution Flowchart

Below is the flowchart that you can use to create FPGA-based motor simulators.

For the first step, you need to collect motor parameters and raw data. Use the floating-point simulation step to verify whether simulation results match the measurement data. You then can utilize the fixed-point simulation step to verify fix-point motor models, such as whether they keep enough precision and produce satisfied results.  After verifying fixed-point models, you can go to the final deployment step.

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5. Ways to Tackle Fixed-Point Implementation Challenges

Motors usually have quite different power ratings. However, the range and precision of fixed-point data type are fixed. Selecting proper fixed-point data types is quite important. Otherwise, the quantization errors will accumulate very quickly and make the simulation results incorrect. It will be difficult to manually adjust and calibrate all the fixed-point configurations to make them best accommodate their own case. National Instruments provides the following solutions to tackle these challenges.

a.      Per-Unit System

Besides using engineering unit, electrical engineers also use per-unit. A per-unit system scales current, voltage, speed, etc, so that their per-unit values at the nominal operating point are near 1.0. This feature of per-unit system makes it ideal for the fixed-point implementation. It helps to make the fixed-point motor model usable for various motors.

After adopting the per-unit system, you can select certain pre-defined fixed-point data types for fixed-point motor models. The following table lists some selections.

 

Word length

Integer word length

Data range

Per unit current

32

5

[-16, 16)

Per unit speed

32

4

[-8, 8)

Per unit voltage

24

4

[-8, 8)

These selections have left some room for some extreme cases, such as over-current.

Determining fixed-point data types for these variables can help you select fixed-point configurations for internal computation units, such as the conversion from Idq to Iabc in the following figure.


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b.      Moving Some Calculations to the Host

The motor simulation process involves some division operations, such as   . These operations don't involve time-varying variables, such as the current. Thus you don’t need to update them for each step.  You can move these division operations to the host and avoid tricky issues of handling the division on FPGA.

So there are two VIs for the fixed-point motor models. One host VI is handling some division operations and parameter conversion jobs. The other FPGA VI is simulating the fixed-point motor model on the target.

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6. Examples

The following figure shows the speed and the electromagnetic torque of a fixed-point PMSM model during speeding up and decelerating phases.


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You can observe the regenerative braking effect during the decelerating phase. The electromagnetic torque is negative, where the motor is feeding the energy back to the DC source (the battery).

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7. Conclusion

This document presents FPGA Programming for motor drive simulators. They can help you build high-speed motor drive HIL testing systems with NI-RIO hardware. 

The source code and examples for the FPGA-based motor drive simulator are available upon request. Please feel free to join and post messages on Motor Simulation User Group if you would like to obtain the code and examples or if you have any questions about this document.

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Customer Reviews
9 Reviews | Submit your review

code request  - Oct 29, 2013

hi, I need the simulation code for my lab research, would you mind send me one to the liangxinyu19911118@gmail.com?

Simulation Tool Kit used  - Sep 27, 2013

Hi, please send me details how you did simulation using FPGA .

  - Apr 19, 2013

HI! I am Working on a similar project. This code will be very helpful for me. Can you please send it to me in this e- mail?! Thank you very much.

Code requiest  - Apr 14, 2013

i need this code for mu project , can you send me it ! best regards

  - Jan 29, 2013

Hello I am Working on a similar project. This code can be a good reference for me. Can you please send it to me in this e-mail?! Thanks.

Request Code  - Jan 24, 2013

Hello I am Working on a similar project. This code can be a good reference for me. Can you please share it?! Thanks.

request code  - Jun 11, 2012

hi there..can u share me with the code? i would really like to try on this. thanks. my email is fwks89@hotmail.com

request code  - Nov 14, 2011

Hi, I am working on a similar system involving a real time simulation of Three level inverter with SVPWM using a CompactRIO. Could you please share the code for reference. Would be very helpful. Thanks, Mitchell A. Moreno m- moreno@uniandes.edu.co or mitchellmoreno89@gmail.com

request code  - Oct 21, 2011

Hi, I am working on a similar system involving an additional H bridge to control field current. Could you please share the code for reference. Would be very helpful. Thanks, Akshay

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