Digital Delay Generator Reference Example for LabVIEW FPGA and R series

Publish Date: May 06, 2010 | 1 Ratings | 3.00 out of 5 | Submit your review

Overview

This example shows how to use a National Instruments Reconfigurable I/O (RIO) board as a digital delay generator and discusses when it is appropriate to do so.

Table of Contents

  1. What is a Digital Delay Generator?
  2. Implementing a Digital Delay Generator using LabVIEW FPGA and Reconfigurable I/O
  3. Things to Consider when Choosing a NI RIO Solution
  4. Comparison
  5. Conclusion
  6. Related Links

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The examples for this article are contained in a LabVIEW 8.6 project in the ZIP file above. Unzip the file on your local hard drive and open the LabVIEW project file.

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1. What is a Digital Delay Generator?

A digital delay generator is a device that provides precise delays for triggering, synching, delaying and gating events, typically at logic level.  In most cases, there is a single input that is used to trigger multiple, individually delayed outputs.  These outputs are often combined to create different pulses/pulse trains.

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2. Implementing a Digital Delay Generator using LabVIEW FPGA and Reconfigurable I/O

In general, the code needs to have the following sequence of events: 

First, wait for an input trigger.  When that trigger is received, individually delay the outputs.  Set the outputs high as their delay times expire.  Once all the outputs have gone high, continue to hold them high for a set time.  After this hold time expires, set all outputs low.   Then, start the process over again by waiting for the next trigger.  See Figure 1 below for a graphic representation of this output logic.

Figure 1. Typical Output Logic for a Digital Delay Generator 

One of the major benefits of a LabVIEW FPGA solution is that you can define the logic to fit your needs.  You can take this base logic, create various output combinations, add channels, add multiple input triggers, add digital pattern matching, etc. without adding extra cost.  A few examples of this flexibility are shown below.

An Example Digital Delay Generator on FPGA

Figure 2 shows one way of implementing the sequence described above.


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Figure 2. Digital Delay Generator Example Block Diagram

The code starts by looking for a rising edge on Trigger.  If none occurs, Count is kept at zero.  This keeps all the outputs at their default levels.  Once a rising edge is detected, Triggered? is set to True.  This starts the counting of loop iterations on the wire labeled Count.  As Count goes above the individual Delay/Channel(Ticks) values, outputs A & B are set high.  Finally, when Count has gone above Total Count (ticks), the line Triggered? is set to False.  This sets the process back to the beginning.  This example can be found in the attached project above.

One item to note in this example is how A & B are combined with an XOR function (exclusive or).  This creates a pulse output that is set high when A or B is high and is set low when the remaining output (A or B) is also set high.  If A & B  are set high at the same time, there will be no pulse.  We also do an inverse of this (AB*).  AB* is always high until one output (A or B) is set high.  When this happens AB* is set low until the remaining output (A or B) is also set high.  These combinatorial outputs are typical for digital delay generators.

An Example of Customization

For an example of customization, see Figure 3 below.


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Figure 3. Advanced Combinatorial Output Digital Delay Generator Example

The triggering and counting operate in the same manner as the previous example and are not shown in Figure 3.  This example implements 16 triggers (A, B, C, etc.) with eight relating pulses (AB, CD, etc) and eight inverted pulses (AB*, CD*, etc.).  Having these extra channels is usually an additional cost when purchasing a box instrument.  With a NI RIO-based solution, this can be implemented with some extra code.  There are also five additional pulse trains being generated.  The first type is the result of combining two pulses using an OR function.  As an example, AB and CD are combined to create AB+CD.  If pulse AB is set high before CD, you will see a pulse matching AB followed by another pulse matching CD.  There are four of these pulse trains (AB+CD, EF+GH, etc.).  The remaining pulse train, All, is an OR combination of all the pulses (AB through OP).  Therefore, if all the pulses trigger in alphabetical order (AB first, then CD, ... then OP), a pulse train results that mimics AB then CD ... then OP.  These pulse trains are typically another additional cost with a box instrument.  Using NI RIO hardware, this is implemented with just extra code.  Other modifications like multiple input triggers, pattern matching, etc. can also be implemented with additional LabVIEW FPGA code.

One more note is that this example uses 37 digital outputs in total.  Another example included in the attached project has 32 triggers, 16 pulses and 16 inverted pulses (64 outputs total).  This makes the total cost per channel and size/space constraints favor a NI RIO-based solution over a box instrument solution.

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3. Things to Consider when Choosing a NI RIO Solution

While the benefits above are reasons to use a NI RIO-based solution over a box instrument, there are also some trade-offs that should be considered.

One area where box instruments surpass a RIO-based solution is in timing resolution. Typical Digital Delay Generators can provide timing with resolution in the picosecond range.  If this is a requirement of your application, do not choose a NI RIO-based solution.  The maximum rate at which a RIO board can sample a digital input is 200 MHz (5 nanoseconds).  The consequence of this is that a trigger may be sampled up to 5 ns later than it arrived.  This can occur when a trigger goes high immediately after being sampled because the code has to wait another 5 ns before sampling again.  The resolution at which outputs can be updated is also 5 ns. Therefore, signal generation can only happen at multiples of this integer value (50 ns, 55 ns, 60 ns, etc.).  

Another thing to consider when sampling at 5 ns (200 MHz) on a FPGA is that there is less time to execute code.  This means sequential code has to be kept at a minimum.  This also limits your RIO board selection to Virtex 5-based devices (NI-784xR, NI-785xR), which are better at compiling code at 200 MHz.  If you need more sequential code or choose to use a different RIO board, you can lower your sample rate to compile the FPGA code.  Doing so will increase your resolution and error.  Sampling at 25 ns (40 MHz) will give a 25 ns resolution with up to a 25 ns error on reading the incoming trigger.

The accuracy and jitter of the FPGA clock should also be considered.  The peak-to-peak jitter of the Virtex 5 FPGA clock is listed in the NI R Series Intelligent DAQ Specifications manual as 250 ps.  Jitter is increased by 150 ps when using a 200 MHz timebase and is increased another 350 ps if phase locked to the PXI 10 MHz clock.  The FPGA clock accuracy is listed as 100 ppm.  This accuracy can be greatly improved by using a PXI Chassis and NI Timing and Sync board.  This is an additional cost but box instruments also have a relatively poor ppm clock with the option of upgrading for an additional cost.  National Instruments offers a timing board with a clock source that is as accurate as a box instrument (1 ppm).  

For more information on clock accuracy and jitter, see the link "What Is Meant by the Stability of an Onboard Clock?" in the Related Links section below as well as the NI R Series Intelligent DAQ Specifications manual.

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4. Comparison

A simple comparison between a NI RIO-based solution and a typical box instrument and is shown in Figure 4.

Figure 4. Digital Delay Generator Comparison

It is important to note that even when purchasing a NI PXI Chassis, Controller, and Timing and Sync Board (1 ppm Timebase Error), the NI configuration would be five times cheaper on a price per channel basis.

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5. Conclusion

Ultimately, the requirements for the application should decide the end solution.  If you need a small number of channels with picosecond resolution, choose a box instrument.  If you need a compact, high channel count system that is flexible and cost effective for your microsecond timing applications, consider the NI LabVIEW FPGA and RIO-based solution.  

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6. Related Links

Knowledgebase 1F5DD5KD: What Is Meant by the Stability of an Onboard Clock?

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Attachments:

FPGA Digital Delay Generator_8.5

Requirements

FPGA Digital Delay Generator_8.6

Requirements


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