FPGA Debug Reference Library

Publish Date: May 06, 2010 | 7 Ratings | 3.57 out of 5 | Print | 2 Customer Reviews | Submit your review


Situations arise in LabVIEW FPGA programming that require debugging the application on the target in real time. The FPGA Debug Library component provides a set of simple, modular, reusable VIs that can be included in a project design to make the debugging process both faster and easier.

Table of Contents

  1. Purpose
  2. The FPGA Debug Library Component
  3. How to Use the FPGA Debug VIs
  4. Discussion and Feedback

1. Purpose

LabVIEW FPGA provides an emulator and simulated I/O to allow designers to debug their applications quickly and easily. Situations do, however, arise that require the code to be compiled to the FPGA target, then run and debugged in real time. For example, when CLIP is included in the LabVIEW Project and linked to the top-level VI through I/O Nodes, the VI can no longer be run in Emulation mode. To characterize its behavior in coordination with the CLIP, the VI must be compiled and run on the target.

In these situations, it is necessary to write additional code into the application for the purpose of testing and validating the application's core functionality. This code is usually removed or disabled when debugging is complete. The NI FPGA Debug Library component provides a set of simple functions that are frequently needed when debugging LabVIEW FPGA applications in real time. In addition to performing common simple tasks, these functions provide a modular programming interface for rapidly constructing advanced debugging structures.

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2. The FPGA Debug Library Component

The NI FPGA Debug Utilities component installs a new library into the <user.lib> folder, called FPGA Debug.lvlib. This library contains all the API VIs and polymorphic instance VIs belonging to the component. The API VIs can be placed on the diagram from the FPGA Debug palette in the User Libraries function palette. By default, the User Libraries palette is not visible from the Functions palette when developing on an FPGA target. To make this palette visible, follow the instructions in KB 4NULKE5M: How Can I Add My Reusable VIs to FPGA Functions Palette?.

FPGA Debug function palette

It also installs two example projects that demonstrate the API's use in a debugging environment. (See below.)

FPGA Debug VIs

FPGA Debug.lvlib contains the following functions:

Counter.vi is a simple numeric counter. It stores a value internally and increments that value every time it is called. The value is provided at the VI's output. It also has an optional input that allows the user to set its initial value.

Count Booleans.vi is a modified counter. It stores a value internally and increments that value every time it is call with the input value equal to a specific Boolean value. This lets it provide at its output the number of times its input signal has held a TRUE or FALSE value.

Detect Edge.vi looks for rising or falling edges on a Boolean signal. If it is called twice with the input value TRUE on the first call and FALSE on the second, it sees a falling edge. If the inputs are reversed (FALSE first, then TRUE), it sees a rising edge. The output becomes TRUE when the selected edge is seen at the input.

Latch Number.vi preserves an instantaneous numeric value. When called with the Latch control set to TRUE, it stores the value at its numeric input. On this and every subsequent call with Latch = FALSE, its output value will remain equal to that latched number. When it is called again with Latch = TRUE, the internal value is overwritten with a new input number.

Latch Boolean.vi preserves a TRUE value on a Boolean signal. A TRUE value will be held at the output for the number of calls specified. (The value can also be held forever in one of the polymorphic instances of this VI.)


Installed Examples

Two example programs are installed by this component. To open them using the NI Example Finder, select "Browse by Directory Structure" and navigate to the FPGA Debug folder. They can also be found at the installation path <lvdir>/examples/FPGA Debug.

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3. How to Use the FPGA Debug VIs

Each of these VIs can be used by itself to provide a simple functionality. For example, one common need in debugging a VI running on the target is to monitor FIFO overflows and underflows. The FIFO Read and Write nodes provide a "Timeout?" output. Simply attaching an indicator to that output and monitoring it from the host application is often inadequate though, because a TRUE value is only asserted in the instant that the node is executed and fails. If it succeeds in the next execution, the output becomes FALSE. To circumvent this, the Latch Boolean VI can be used to ensure that the TRUE value is held long enough for the host to detect and display it to the user.

Use the Latch Boolean VI to preserve FIFO overflow and underflow flags for the host application.

The FPGA Debug VIs can also be used in combination to create complex structures for debugging and validation. In this example, three of the functions (Detect Edge, Count Booleans, and Latch Number) are used to quickly implement a Buffered Event Counter that watches for falling-edge events on the target's I/O pins. By removing the Latch Number VI, the same code can be converted to a simple Count Edges function.

Use the VIs together to create complex structures like these advanced I/O Counters.

More examples of how to utilize the VIs in this component can be found in the installed example Use Cases.lvproj.

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4. Discussion and Feedback

This component was created by the NI Systems Engineering group.

We welcome discussion and feedback about this component. The FPGA Debug Library thread is available on the NI Discussion Forums for questions, comments, and suggestions.


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Customer Reviews
2 Reviews | Submit your review

Small, nice, very helpful  - Mar 20, 2016

Thanks for that little Library

Comment on the FPGA Debug Library thread as well  - Oct 17, 2008

Make sure you comment on the FPGA Debug Library thread http://forums.ni.com/ni/board/message?board.id=Components&thread.id=60 as well. Comments posted there will be read and responded to.

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